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* ti: common: board_detect: Rename EEPROM scratch start macroLokesh Vutla2017-03-201-3/+5
| | | | | | | | | Non OMAP platforms i.e. Keystone will also need to use the board EEPROM helpers so let's make the macro platform independent. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5+: GPIO: Add GPIO_TO_PIN() macroRoger Quadros2017-03-201-0/+4
| | | | | | | | | GPIO_TO_PIN(bank, bank_gpio) returns the GPIO index from the GPIO bank number and bank's GPIO offset number. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* ti: boot: Register the MMC controllers in SPL in the same way as in u-bootJean-Jacques Hiblot2017-03-192-16/+1
| | | | | | | | | | | | To keep a consistent MMC device mapping in SPL and in u-boot, let's register the MMC controllers the same way in u-boot and in the SPL. In terms of boot time, it doesn't hurt to register more controllers than needed because the MMC device is initialized only prior being accessed for the first time. Having the same device mapping in SPL and u-boot allows us to use the environment in SPL whatever the MMC boot device. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-03-1950-164/+8934
|\ | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/bk4r1_defconfig configs/colibri_vf_defconfig configs/pcm052_defconfig include/configs/colibri_vf.h include/configs/pcm052.h
| * ARM: vf610: move to standard arch/board approachStefan Agner2017-03-192-25/+40
| | | | | | | | | | | | | | | | Move Freescale/NXP Vybrid to a standard arch/board approach, similar to what has been done to i.MX 6 earlier in commit 89ebc82137be ("ARM: mx6: move to a standard arch/board approach"). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * mx7: Add 1.2GHz speed grade entryFabio Estevam2017-03-191-0/+3
| | | | | | | | | | | | | | | | There are recent MX7 parts that have a 1.2GHz speed grade. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7: Fix the get_cpu_speed_grade_hz() return valuesFabio Estevam2017-03-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the MX7D fuse map the following speed grades are available: 800 MHz 500 MHz 1000 MHz 1200 MHz So simply return the real frequency that corresponds to the speed grade. With this change we see on boot: CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz) Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * mx7: Fix speed grade entryFabio Estevam2017-03-191-3/+3
| | | | | | | | | | | | | | According to the MX7D fuse map the speed grade of the parts, which return '1' is 500MHz instead of 850MHz, so fix it accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
| * arm: dts: imx6ul: add usbotg aliasesSébastien Szymanski2017-03-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed to make the UMS command work again as it fails with the following error: BIOS> ums 0 mmc 0 UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x748000 g_dnl_register: failed!, error: -19 ERROR: g_dnl_register failed at cmd/usb_mass_storage.c:179/do_usb_mass_storage() That's because usb_setup_ehci_gadget() function is looking for the usb device using the req_sed number. This change makes the usb device have a req_seq number and the UMS command work again: BIOS> ums 0 mmc 0 UMS: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x748000 CTRL+C - Operation aborted Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
| * arm: i.MX6UL: add Armadeus Systems OPOS6UL SoM and OPOS6ULDev carrier boardSébastien Szymanski2017-03-197-1/+940
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet phy. OPOS6ULDev is carrier board for the OPOS6UL. U-Boot SPL 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09) Trying to boot from MMC1 U-Boot 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09 +0100) CPU: Freescale i.MX6UL rev1.0 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 40C Reset cause: POR Model: Armadeus Systems OPOS6UL SoM on OPOS6ULDev board DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Video: 800x480x18 In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: dts: imx6qdl-icore-rqs: Add eMMC nodeJagan Teki2017-03-171-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usdhc4 node, which is eMMC for Engicam i.CoreM6 RQS modules. eMMC Log: -------- icorem6qdl-rqs> mmc dev 1 switch to partitions #0, OK mmc1(part 0) is current device icorem6qdl-rqs> mmcinfo Device: FSL_SDHC Manufacturer ID: fe OEM: 14e Name: MMC04 Tran Speed: 52000000 Rd Block Len: 512 MMC version 4.4.1 High Capacity: Yes Capacity: 3.5 GiB Bus Width: 4-bit Erase Group Size: 512 KiB HC WP Group Size: 4 MiB User Capacity: 3.5 GiB Boot Capacity: 16 MiB ENH RPMB Capacity: 128 KiB ENH Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * i.MX6UL: isiot: Add eMMC boot supportJagan Teki2017-03-172-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot from eMMC: -------------- U-Boot SPL 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27) Trying to boot from MMC2 U-Boot 2017.01-00314-gd0cd9cd-dirty (Jan 25 2017 - 13:25:27 +0100) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 36C Reset cause: POR Model: Engicam Is.IoT MX6UL eMMC Starterkit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial switch to partitions #0, OK mmc1(part 0) is current device Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: Add src_base structure define macroJagan Teki2017-03-174-9/+6
| | | | | | | | | | | | | | | | Instead of initializing 'struct src' to SRC_BASE_ADDR on every function better to have global define macro. Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@openedev.com>
| * imx: Use IMX6_BMODE_* macros instead of numericalsJagan Teki2017-03-172-15/+60
| | | | | | | | | | | | | | | | | | Use meaningful macros IMX6_BMODE_*, instead of numerical number in boot mode detection code. Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@openedev.com>
| * imx: spl: Update NAND bootmode detection bitJagan Teki2017-03-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | BOOT_CFG1[7:4] the NAND boot mode selection is done only when BOOT_CFG1[7] is 1 hence update the NAND boot mode detection bit case. This information available on Table 8-11. NAND Boot eFUSE Descriptions, from IMX6DQRM. Cc: Tim Harvey <tharvey@gateworks.com> Reviewed by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@openedev.com>
| * imx6: Add imx6_src_get_boot_modeJagan Teki2017-03-173-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For i.MX6, the bootmode determine code is part of spl_boot_device, but there is might be a possibility for other part the code need to check the desired boot mode for adding new functionalities like modeboot env variable, or changing boot order etc. So introduced imx6_src_get_boot_mode which actually reading the boot mode register for desired modes. More cleanup will be add in future patches. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx6: isiotmx6ul: Add NAND supportJagan Teki2017-03-172-1/+52
| | | | | | | | | | | | | | | | | | Add NAND support for Engicam Is.IoT MX6UL board. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: isiotmx6ul: Add FEC supportJagan Teki2017-03-171-0/+1
| | | | | | | | | | | | | | | | | | Add FEC support for Engicam Is.IoT MX6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: dts: imx6ul-isiot: Add FEC nodeJagan Teki2017-03-171-0/+22
| | | | | | | | | | | | | | | | | | Add FEC node for Engicam Is.IoT MX6UL module. Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx6: isiotmx6ul: Add I2C supportJagan Teki2017-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C support for Engicam Is.IoT MX6UL module. isiotmx6ul> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 isiotmx6ul> i2c dev 0 Setting bus to 0 isiotmx6ul> i2c dev Current bus is 0 isiotmx6ul> i2c speed 100000 Setting bus speed to 100000 Hz isiotmx6ul> i2c probe Valid chip addresses: 00 2C 44 78 isiotmx6ul> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: dts: imx6ul-isiot: Add I2C nodesJagan Teki2017-03-171-0/+28
| | | | | | | | | | | | | | | | | | Add I2C nodes for Engicam Is.IoT MX6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial supportJagan Teki2017-03-174-1/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot from MMC: ------------- U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33) Trying to boot from MMC1 U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 33C Reset cause: POR Model: Engicam Is.IoT MX6UL Starterkit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 isiotmx6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * imx: imx7ulp: add EVK board supportPeng Fan2017-03-174-0/+482
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add EVK board support. Add the evk dts file. LOG: U-Boot 2017.03-rc2-00038-gab86c1d (Feb 22 2017 - 15:59:58 +0800) CPU: Freescale i.MX7ULP rev1.0 at 500 MHz Reset cause: POR Boot mode: Dual boot Model: NXP i.MX7ULP EVK DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial@402D0000 Out: serial@402D0000 Err: serial@402D0000 Net: Net Initialization Skipped No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * arm: dts: add i.MX7ULP dtsi filePeng Fan2017-03-172-0/+1480
| | | | | | | | | | | | | | | | Add i.MX7ULP dtsi file. Add clock and pinfun header files. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * mx7ulp: Add HAB boot supportPeng Fan2017-03-174-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF size for HAB support boot on mx7ulp. Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build secure uboot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
| * serial: lpuart: restructure lpuart driverPeng Fan2017-03-175-110/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop CONFIG_LPUART_32B_REG. Move the register structure to a common file include/fsl_lpuart.h Define lpuart_serial_platdata structure which includes the reg base and flags. For 32Bit register access, use lpuart_read32/lpuart_write32 which handles big/little endian. For 8Bit register access, still use the orignal code. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: York Sun <york.sun@nxp.com> Cc: Shaohui Xie <Shaohui.Xie@nxp.com> Cc: Alison Wang <b18965@freescale.com>
| * i2c: lpi2c: add lpi2c driver for i.MX7ULPPeng Fan2017-03-171-0/+520
| | | | | | | | | | | | | | | | | | | | | | Add lpi2c driver for i.MX7ULP. Need to enable the two options to use this driver: CONFIG_DM_I2C=y CONFIG_SYS_I2C_IMX_LPI2C=y Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * mx7ulp: Add iomux pins header fileYe Li2017-03-171-0/+910
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins to add IOMUX_CONFIG_MPORTS flags. Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address to aligin with it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * mxc_ocotp: Update driver to support OCOTP controller on i.MX7ULPPeng Fan2017-03-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Update the mxc_ocotp driver to support i.MX7ULP. The read/write sequence has some changes due to PDN and OUT_STATUS registers added and TIME register is removed. Also update the bank size and number. Add is_mx7ulp macro in sys_proto.h Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
| * gpio: Add Rapid GPIO2P driver for i.MX7ULPPeng Fan2017-03-171-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP. Have added all ports on RGPIO2P_0 and RGPIO2P_1. The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set to y to enable the drivers. To use the GPIO function, the IBE and OBE needs to set in IOMUXC. We did not set the bits in driver, but leave them to IOMUXC settings of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number for gpio APIs access. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
| * imx: mx7ulp: Implement the clock functions for i2c driverYe Li2017-03-172-0/+44
| | | | | | | | | | | | | | | | | | Implement the i2c clock enable and get function for mx7ulp. These functions are required by imx_lpi2c driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx: mx7ulp: Add soc level initialization codes and functionsPeng Fan2017-03-176-2/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Reuse some code in imx-common. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx7ulp: Add clock framework and functionsPeng Fan2017-03-177-1/+2441
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1Peng Fan2017-03-173-0/+173
| | | | | | | | | | | | | | | | | | | | | | | | Add a new driver under ULP directory to support its IOMUXC controllers. The ULP has two IOMUXC, the IOMUXC0 is used for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as the default IOMUX in this driver. Any pins in IOMUXC0 needs to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
| * imx: mx7ulp: add registers header filePeng Fan2017-03-171-0/+1120
| | | | | | | | | | | | | | | | | | Add imx-regs.h for i.MX7ULP registers addresses definitions and some registers structures. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
| * imx: mx7ulp: Add mx7ulp to KconfigPeng Fan2017-03-173-1/+15
| | | | | | | | | | | | | | | | | | | | i.MX7ULP is a new series SoC which has different architecture from previous i.MX platforms. Create a new cpu folder for it, and add it to Kconfig. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de>
* | arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILDTom Rini2017-03-1818-20/+57
| | | | | | | | | | | | | | | | | | | | | | | | Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for various reasons. We also have cases where we only build SPL in Thumb2 mode due to size constraints and wish to build the rest of the system in ARM mode. So in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to control if we build everything or just SPL (or in theory, just U-Boot) in Thumb2 mode. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2017-03-1750-37/+8754
|\ \ | | | | | | | | | | | | | | | This includes support for rk3188 from Heiko Stübner and and rk3328 from Kever Yang. Also included is SPL support for rk3399 and a fix for rk3288 to get it booting again (spl_early_init()).
| * | rockchip: dts: tinker: add usb host power supply nodeEddie Cai2017-03-162-0/+23
| | | | | | | | | | | | | | | | | | | | | Tinker board have a usb host. add dts node to provide power supply. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3036: dts: bind usb vbus-supply sourceKever Yang2017-03-161-0/+2
| | | | | | | | | | | | | | | | | | | | | Bind usb host and otg vbus to its source. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | ARM: dts: rockchip: enable gmac for rk3288 boardsJacob Chen2017-03-163-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | Enable gmac interface for rk3288 board dts. use "okay" not "ok" Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | dts: rk3036: add sdmmc for rk3036Eddie Cai2017-03-161-0/+13
| | | | | | | | | | | | | | | | | | | | | rk3036 support sdmmc, add dts node to support it. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | dts: rk3399: add mmc alias for rk3399Eddie Cai2017-03-161-0/+2
| | | | | | | | | | | | | | | | | | | | | add mmc alias for rk3399 Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3328: add evb-rk3328 supportKever Yang2017-03-161-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | evb-rk3328 is an evb from Rockchip based on rk3328 SoC: - 2 USB2.0 Host port; - 1 USB3.0 Host port; - 1 HDMI port; - 2 10/100M eth port; - 2GB ddr; - 16GB eMMC; - UART to USB debug port; Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3328: add pinctrl driverKever Yang2017-03-161-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | Add rk3328 pinctrl driver and grf/iomux structure definition. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3328: add clock driverKever Yang2017-03-163-0/+102
| | | | | | | | | | | | | | | | | | | | | Add rk3328 clock driver and cru structure definition. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3328: add soc basic supportKever Yang2017-03-166-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RK3328 is a SoC from Rockchip with quad-core Cortex-A53 CPU. It supports two USB2.0 EHCI ports. Other interfaces are very much like RK3288, the DRAM are 32bit width address and support address from 0 to 4GB-16MB range. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Add empty arch/arm/mach-rockchip/rk3328/Kconfig to avoid build error: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3328: add device tree fileKever Yang2017-03-163-0/+1523
| | | | | | | | | | | | | | | | | | | | | | | | Add dts binding header for rk3328, files origin from kernel. Signed-off-by: William Zhang <william.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: config: rk3399: enable SPL config for evb-rk3399Kever Yang2017-03-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable all the CONFIGs which need by SPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Added rockchip tag: Drop CONFIG_ROCKCHIP_DWMMC for now due to build error: Move changes to arch/arm/mach-rockchip/Kconfig to this patch: Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: arm64: rk3399: add SPL supportKever Yang2017-03-162-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPL support for rk3399, default with of-platdata enabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Drop Kconfig changes to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org>
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