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* gpio: remove the open_drain API and opsPatrick Delaunay2020-04-161-20/+0
| | | | | | | | | | | | | | This patch removes the ops get_open_drain/set_open_drain and the API dm_gpio_get_open_drain/dm_gpio_set_open_drain. The ops only provided in one driver (mpc8xxx gpio) and the associated API is never called in boards. This patch prepare a more generic set/get_dir_flags ops, including the open drain property. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* Merge tag 'arc-fixes-for-2020.07-rc1' of ↵Tom Rini2020-04-163-9/+123
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-arc This is pretty minor set of changes mostly touching HSDK board: * Enable on-chip reset controller on HSDK * Add possibility to turn-on & off L2$ on more recent ARC HS processors. * AXI tunnel clock calculation on HSDK
| * ARC: HSDK: Enable on-chip reset controllerEugeniy Paltsev2020-04-161-0/+7
| | | | | | | | | | | | | | | | As the driver of on-chip reset controller became available we are ready to enable it. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * ARC: CACHE: mark IOC helper functions as inlined_cachefuncEugeniy Paltsev2020-04-161-3/+3
| | | | | | | | | | | | | | | | Force inlining of IOC related functions used in other cache functions. This is preventive change. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * ARC: CACHE: add support for SL$ disableEugeniy Paltsev2020-04-162-7/+114
| | | | | | | | | | | | | | | | Since version 3.0 ARC HS supports SL$ (L2 system level cache) disable. So add support for SL$ disable/enable to code. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge tag 'dm-pull-10apr20-take2' of git://git.denx.de/u-boot-dmTom Rini2020-04-166-8/+64
|\ \ | |/ |/| | | | | | | | | | | Functions for reading indexed values from device tree Enhancements to 'dm' command Log test enhancements and syslog driver DM change to read parent ofdata before children Minor fixes
| * dm: core: support reading a single indexed u32 valueDario Binacchi2020-04-161-0/+1
| | | | | | | | | | | | | | | | | | The patch adds helper functions to allow reading a single indexed u32 value from a device-tree property containing multiple u32 values, that is an array of integers. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dm: test: add test case for dev_read_u64 functionDario Binacchi2020-04-161-0/+1
| | | | | | | | | | | | | | Add test case to cover dev_read_u64 and dev_read_u64_default functions. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: implement ft_board_setup()Heinrich Schuchardt2020-04-161-0/+1
| | | | | | | | | | | | | | | | | | | | Currently we are not able to test reservations created by ft_board_setup(). Implement ft_board_setup() to create an arbitrary reservation and enable OF_BOARD_SETUP. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromum.org>
| * sandbox: add reserved-memory node in device treeHeinrich Schuchardt2020-04-162-0/+39
| | | | | | | | | | | | | | | | For testing the handling of memory reservations create a reserved-memory node in sandbox.dts and sandbox64.dts. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromum.org>
| * sandbox: also restore terminal settings when killed by SIGINTRasmus Villemoes2020-04-161-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hitting Ctrl-C is a documented way to exit the sandbox, but it is not actually equivalent to the reset command. The latter, since it follows normal process exit, takes care to reset terminal settings and restoring the O_NONBLOCK behaviour of stdin (and, in a terminal, that is usually the same file description as stdout and stderr, i.e. some /dev/pts/NN). Failure to restore (remove) O_NONBLOCK from stdout/stderr can cause very surprising and hard to debug problems back in the terminal. For example, I had "make -j8" consistently failing without much information about just exactly what went wrong, but sometimes I did get a "echo: write error". I was at first afraid my disk was getting bad, but then a simple "dmesg" _also_ failed with write error - so it was writing to the terminal that was buggered. And both "make -j8" and dmesg in another terminal window worked just fine. So install a SIGINT handler so that if the chosen terminal mode (cooked or raw-with-sigs) means Ctrl-C sends a SIGINT, we will still call os_fd_restore(), then reraise the signal and die as usual from SIGINT. Before: $ grep flags /proc/$$/fdinfo/1 flags: 0102002 $ ./u-boot # hit Ctrl-C $ grep flags /proc/$$/fdinfo/1 flags: 0106002 After: $ grep flags /proc/$$/fdinfo/1 flags: 0102002 $ ./u-boot # hit Ctrl-C $ grep flags /proc/$$/fdinfo/1 flags: 0102002 Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: Update PCI nodes in dts filesTom Rini2020-04-164-8/+13
| | | | | | | | | | | | | | | | | | | | | | The way the PCI nodes are written today causes a number of warnings if we stop disabling some of the warnings we pass to DTC. As these warnings aren't disabled in current Linux Kernel builds, we should aim to not disable them here either, so rewrite these slightly. Update the driver model doc as well. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | x86: Move acpi_table header to main include/ directorySimon Glass2020-04-1610-384/+17
| | | | | | | | | | | | | | | | | | This file is potentially useful to other architectures saddled with ACPI so move most of its contents to a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
* | x86: Move acpi_s3.h to include/acpi/Simon Glass2020-04-1611-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This header relates to ACPI and we are about to add some more ACPI headers. Move this one into a new directory so they are together. The header inclusion in pci_rom.c is not specific to x86 anymore, so drop the #ifdef CONFIG_X86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | acpi: Add a simple sandbox testSimon Glass2020-04-162-0/+13
| | | | | | | | | | | | | | | | Add a sandbox test for the basic ACPI functionality we have so far. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
* | x86: apl: Add Global NVS table headerSimon Glass2020-04-161-0/+36
| | | | | | | | | | | | | | | | Add the C version of this header. It includes a few Chrome OS bits which are disabled for a normal build. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolgang.wallner@br-automation.com>
* | x86: apl: Move p2sb ofdata reading to the correct methodSimon Glass2020-04-161-22/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
* | x86: Correct wording of coreboot source codeSimon Glass2020-04-163-6/+4
| | | | | | | | | | | | | | | | | | Some files are taken or modified from coreboot, but the files are no-longer part of the coreboot project. Fix the wording in a few places. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
* | tpm: cr50: Use the correct GPIO bindingSimon Glass2020-04-161-1/+1
| | | | | | | | | | | | | | This device should use ready-gpios rather than ready-gpio. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: acpi: Let OS know that console already had been initializedAndy Shevchenko2020-04-161-0/+9
|/ | | | | | | | | | | | | | SPCR has no clue if the UART base clock speed is different to the default one. However, the SPCR 1.04 defines baud rate 0 as a preconfigured state of UART and OS is supposed not to touch the configuration of the serial device. Linux kernel supports that starting from v5.0, see commit b413b1abeb21 ("ACPI: SPCR: Consider baud rate 0 as preconfigured state") for the details. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: dts: stm32: Rename LEDs to match silkscreen on AV96Marek Vasut2020-04-151-3/+3
| | | | | | | | | | | The LED labels do not match the silkscreen on the board, fix it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* configs: stm32mp1: replace STM32MP1_TRUSTED by TFABOOTPatrick Delaunay2020-04-154-29/+21
| | | | | | | | | | | | Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT introduced by the commit 535d76a12150 ("armv8: layerscape: Add TFABOOT support"). This config CONFIG_TFABOOT is activated for the trusted boot chain, when U-Boot is loaded by TF-A. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* ARM: dts: stm32: Add KS8851-16MLL ethernet on FMC2Marek Vasut2020-04-151-0/+68
| | | | | | | | | | | Add DT entries, Kconfig entries and board-specific entries to configure FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* ARM: dts: stm32: Define FMC2 base addressMarek Vasut2020-04-151-0/+1
| | | | | | | | | | | Define FMC2 base address, for use in board files, until there is an actual FMC2 bus driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* Merge branch 'master' of git://git.denx.de/u-boot-marvellWIP/14Apr2020Tom Rini2020-04-1413-86/+418
|\ | | | | | | | | | | | | - Misc enhancements to Clearfog, including board variant detection (Joel) - Misc enhancements to Turris Mox, including generalization of the ARMADA37xx DDR size detection (Marek)
| * arm64: mvebu: a37xx: add device-tree fixer for PCIe regionsMarek Behún2020-04-142-0/+55
| | | | | | | | | | | | | | | | | | | | | | In case when ARM Trusted Firmware changes the default address of PCIe regions (which can be done for devices with 4 GB RAM to maximize the amount of RAM the device can use) we add code that looks at how ATF changed the PCIe windows in the CPU Address Decoder and changes given device-tree blob accordingly. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: a37xx: improve code determining memory info structuresMarek Behún2020-04-143-26/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently on Armada-37xx the mem_map structure is statically defined to map first 2 GB of memory as RAM region, and system registers and PCIe region device region. This is insufficient for when there is more RAM or when for example the PCIe windows is mapped to another address by the CPU Address Decoder. In the case when the board has 4 GB RAM, on some boards the ARM Trusted Firmware can move the PCIe window to another address, in order to maximize possible usable RAM. Also the dram_init and dram_init_banksize looks for information in device-tree, and therefore different device trees are needed for boards with different RAM sizes. Therefore we add code that looks at how the ARM Trusted Firmware has configured the CPU Address Decoder windows, and then we update the mem_map structure and compute gd->ram_size and gd->bd->bi_dram bank base addresses and sizes accordingly. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: armada-8k: move dram init codeMarek Behún2020-04-144-46/+59
| | | | | | | | | | | | | | | | Move Armada-8k specific DRAM init code into armada-8k specific directory. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: dts: turris_mox: fix USB3 regulatorMarek Behún2020-04-141-0/+1
| | | | | | | | | | | | | | | | | | | | Commit e8e9715df2d4 requires the USB3 regulator node to have the enable-active-high property for the regulator to work properly. The GPIO_ACTIVE_HIGH constant is not enough anymore. Signed-off-by: Marek Behún <marek.behun@nic.cz> Fixes: e8e9715df2d4 ("regulator: fixed: Modify enable-active-high...") Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: dts: turris_mox: update sdhci propertiesMarek Behún2020-04-141-0/+18
| | | | | | | | | | | | | | | | With recent changes to the mmc subsystem (chip detect code etc) update the sdhci node of the Turris Mox device tree. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: clearfog: initial ClearFog Base variantJoel Johnson2020-04-141-0/+2
| | | | | | | | | | | | | | | | Add a unique entry for ClearFog Base variant, reflected in the board name and adjusted SerDes topology. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: solidrun: remove hardcoded DTS MAC addressJoel Johnson2020-04-141-1/+0
| | | | | | | | | | | | | | | | | | Using a consistent hardcoded MAC address from the DTS file causes issues when using multiple devices on the same network segment. Instead rely on environment configuration or random generation. Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: fix SerDes table alignmentJoel Johnson2020-04-141-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested on Solidrun ClearFog Base. Table alignment was: | Lane # | Speed | Type | -------------------------------- | 0 | 3 | SATA0 | | 1 | 0 | SGMII1 | | 2 | 3 | SATA1 | | 3 | 5 | USB3 HOST1 | | 4 | 5 | USB3 HOST0 | | 5 | 4 | SGMII2 | -------------------------------- After the change, it's correctly aligned as: | Lane # | Speed | Type | -------------------------------- | 0 | 3 | SATA0 | | 1 | 0 | SGMII1 | | 2 | 5 | PCIe1 | | 3 | 5 | USB3 HOST1 | | 4 | 5 | PCIe2 | | 5 | 0 | SGMII2 | -------------------------------- Signed-off-by: Joel Johnson <mrjoel@lixil.net> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: update RTC values for PCIe memory wrappersChris Packham2020-04-144-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the RTC (Read Timing Control) values for PCIe memory wrappers following an ERRATA (ERRATA# TDB). This means the PCIe accesses will used slower memory Read Timing, to allow more efficient energy consumption, in order to lower the minimum VDD of the memory. Will lead to more robust memory when voltage drop occurs (VDDSEG) The code is based on changes from Marvell's U-Boot, specifically: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/20cd2704072512de176e048970f2883db901674b https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/eb608a7c8dd0d42b87601a61b9c0cc5615ab94b2 https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/c4af19ae2bf08cf6e450e741ce4f04d402a5cb6b Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: dts: Sort Armada series dts alphabeticallyJosip Kelecic2020-04-141-10/+10
| | | | | | | | | | | | | | | | | | Sort the Armada series dts in the Makefile alphabetically prior to adding new board support. Signed-off-by: Josip Kelečić <josip.kelecic@sartura.hr> Reviewed-by: Luka Kovacic <luka.kovacic@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaWIP/13Apr2020Tom Rini2020-04-138-146/+303
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| * arm: socfpga: arria10: Enable cache driver in SPLLey Foon Tan2020-04-132-0/+5
| | | | | | | | | | | | | | | | | | | | Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE to enable cache driver in SPL. This fixed error below in SPL: cache controller driver NOT found! Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: dts: arria10: Update dtsi/dts from LinuxLey Foon Tan2020-04-134-56/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update these 3 files from Linux:. - socfpga_arria10.dtsi (Commit ID c1459a9d7e92) - socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b) - socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f) Change in socfpga_arria10.dtsi: - Add clkmgr label, so that can reference to it in u-boot.dtsi. Change in socfpga_arria10-u-boot.dtsi: - Add compatible and altr,sysmgr-syscon for uboot. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * arm: dts: arria10: Move uboot specific properties to u-boot.dtsiLey Foon Tan2020-04-136-92/+186
| | | | | | | | | | | | | | Move Uboot specific properties to *u-boot.dtsi files. Preparation to sync Arria 10 device tree from Linux. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: socfpga: Enable DM RTC bootcount on ABB SECU1Marek Vasut2020-04-131-0/+6
| | | | | | | | | | | | | | | | | | Add and enable RTC-backed boot counter on ABB SECU1 platform. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | Merge branch 'next'Tom Rini2020-04-13155-2175/+6238
|\ \ | |/ |/| | | | | | | | | | | | | | | | | Pull in changes that have been pending in our 'next' branch. This includes: - A large number of CI improvements including moving to gcc-9.2 for all platforms. - amlogic, xilinx, stm32, TI SoC updates - USB and i2c subsystem updtaes - Re-sync Kbuild/etc logic with v4.19 of the Linux kernel. - RSA key handling improvements
| * kconfig / kbuild: Re-sync with Linux 4.19Tom Rini2020-04-107-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align Kconfig and Kbuild logic to Linux 4.19 release with minimal impact on files outside of this scope. Our previous Kconfig sync was done by commit 5972ff077e0f ("kconfig / kbuild: re-sync with Linux 4.18"). In this particular re-sync in order to keep clang support working a number of related changes needed to be pulled in that had been missed previously. Not all of these changes we easily traceable and so have been omitted from the list below. The imported Linux commits are: [From prior to v4.18] 9f3f1fd29976 kbuild: Add __cc-option macro d7f14c66c273 kbuild: Enable Large File Support for hostprogs 6d79a7b424a5 kbuild: suppress warnings from 'getconf LFS_*' 24403874316a Shared library support 86a9df597cdd kbuild: fix linker feature test macros when cross compiling with Clang 0294e6f4a000 kbuild: simplify ld-option implementation [From v4.18 to v4.19] 96f14fe738b6 kbuild: Rename HOSTCFLAGS to KBUILD_HOSTCFLAGS 10844aebf448 kbuild: Rename HOSTCXXFLAGS to KBUILD_HOSTCXXFLAGS b90a368000ab kbuild: Rename HOSTLDFLAGS to KBUILD_HOSTLDFLAGS 8377bd2b9ee1 kbuild: Rename HOST_LOADLIBES to KBUILD_HOSTLDLIBS f92d19e0ef9b kbuild: Use HOST*FLAGS options from the command line 4ab3b80159d4 kconfig: check for pkg-config on make {menu,n,g,x}config 693359f7ac90 kconfig: rename SYMBOL_AUTO to SYMBOL_NO_WRITE f60b992e30ff kbuild: replace $(LDFLAGS) $(ldflags-y) with $(ld_flags) 2fb9279f2c3e kbuild: change ld_flags to contain LDFLAGS_$(@F) c931d34ea085 arm64: build with baremetal linker target instead of Linux when available 5accd7f3360e kconfig: handle format string before calling conf_message_callback() a2ff4040151a kconfig: rename file_write_dep and move it to confdata.c 0608182ad542 kconfig: split out useful helpers in confdata.c adc18acf42a1 kconfig: remove unneeded directory generation from local*config 79123b1389cc kconfig: create directories needed for syncconfig by itself 16952b77d8b5 kconfig: make syncconfig update .config regardless of sym_change_count d6c6ab93e17f kbuild: remove deprecated host-progs variable 56869d45e364 kconfig: fix the rule of mainmenu_stmt symbol c151272d1687 kconfig: remove unused sym_get_env_prop() function 1880861226c1 kconfig: remove P_ENV property type e3fd9b5384f3 scripts/dtc: consolidate include path options in Makefile 4bf6a9af0e91 kconfig: add build-only configurator targets f1575595d156 kconfig: error out when seeing recursive dependency 5e8c5299d315 kconfig: report recursive dependency involving 'imply' f498926c47aa kconfig: improve the recursive dependency report 98a4afbfafd2 kconfig: fix "Can't open ..." in parallel build 9a9ddcf47831 kconfig: suppress "configuration written to .config" for syncconfig 87a32e624037 kbuild: pass LDFLAGS to recordmcount.pl d503ac531a52 kbuild: rename LDFLAGS to KBUILD_LDFLAGS 217c3e019675 disable stringop truncation warnings for now bc8d2e20a3eb kconfig: remove a spurious self-assignment fd65465b7016 kconfig: do not require pkg-config on make {menu,n}config 5a4630aadb9a ftrace: Build with CPPFLAGS to get -Qunused-arguments Note that this adds new cleanup work to do in that we should adapt the shared library support we have to what is now upstream. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Masahiro Yamada <masahiroy@kernel.org>
| * Merge tag 'u-boot-amlogic-20200406' of ↵WIP/08Apr2020-nextTom Rini2020-04-0834-557/+2541
| |\ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic into next - clk: meson-g12a: missing break - sync all Amlogic DT from Linux v5.6-rc2 - MMC clock fixups - add support for Libre Computer AML-S905D-PC and AML-S912-PC
| | * arm64: dts: meson: add libretech-pc supportJerome Brunet2020-04-063-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Amlogic based libretech-pc platform. This platform comes with 2 variant, based on the s905d or s912 SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: update board/amlogic/q200/MAINTAINERS] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| | * arm64: dts: meson: import libretech-pc from linux v5.6-rc2Jerome Brunet2020-04-064-0/+465
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the libretech-pc device tree from Linux v5.6-rc2 11a48a5a18c6 ("Linux 5.6-rc2") Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| | * arm64: dts: meson: sync dt and bindings from v5.6-rc2Jerome Brunet2020-04-0627-557/+2060
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the device tree and dt-bindings from Linux v5.6-rc2 11a48a5a18c6 ("Linux 5.6-rc2") The only exception to this is the mmc pinctrl pin bias of gxl SoC family. This is a fix which found its way to u-boot but not Linux yet. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | Merge tag 'xilinx-for-v2020.07' of ↵WIP/07Apr2020-nextTom Rini2020-04-0785-882/+2208
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2020.07 common: - Align ENV_FAT_INTERFACE - Fix MAC address source print log - Improve based autodetection code xilinx: - Enable netconsole Microblaze: - Setup default ENV_OFFSET/ENV_SECT_SIZE Zynq: - Multiple DT updates/fixes - Use DEVICE_TREE environment variable for DTB selection - Switch to single zynq configuration - Enable NOR flash via DM - Minor SPL print removal - Enable i2c mux driver ZynqMP: - Print multiboot register - Enable cache commands in mini mtest - Multiple DT updates/fixes - Fix firmware probing when driver is not enabled - Specify 3rd backup RAM boot mode in SPL - Add SPL support for zcu102 v1.1 and zcu111 revA - Redesign debug uart enabling and psu_init delay - Enable full u-boot run from EL3 - Enable u-boot.itb generation without ATF with U-Boot in EL3 Versal: - Enable distro default - Enable others SPI flashes - Enable systems without DDR Drivers: - Gem: - Flush memory after freeing - Handle mdio bus separately - Watchdog: - Get rid of unused global data pointer - Enable window watchdog timer - Serial: - Change reinitialization logic in zynq serial driver Signed-off-by: Tom Rini <trini@konsulko.com>
| | * | arm64: versal: Disable DDR cache mapping if DDR is not enabledMichal Simek2020-04-062-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar change was done in past by commit 3b644a3c2f69 ("arm64: zynqmp: Provide a config to not map DDR region in MMU table"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | arm64: zynqmp: Add support for u-boot.itb generation without ATFMichal Simek2020-04-061-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If ATF doesn't exist generate u-boot.itb without it and let U-Boot run in EL3. Still keep warning to let user know that ATF/BL31 is missing. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | arm64: zynqmp: Move timeout for clock propagation below psu_initMichal Simek2020-04-061-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Delay required for clock propagation is tighly coupled with initialization done in psu_init(). That's why call it also for u-boot proper with CONFIG_ZYNQMP_PSU_INIT_ENABLED enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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