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* sunxi: dts: sync Allwinner V3s-related DTs from Linux 5.10-rc1Icenowy Zheng2020-11-176-30/+725
| | | | | | | | This commit imports device tree files that are related to Allwinner V3 series from Linux commit 3650b228f83a ("Linux 5.10-rc1"). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* sunxi: allow to use AXP20[39] attached to I2C0 on V3 seriesIcenowy Zheng2020-11-171-0/+1
| | | | | | | | | | | The reference design of Allwinner V3 series uses an AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the first community-available V3s board, Lichee Pi Zero, omitted it. Allow to introduce support for the PMIC on boards with it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* sunxi: add V3/S3 supportIcenowy Zheng2020-11-171-2/+1
| | | | | | | | | | | | Allwinner V3/Sochip S3 uses the same die with Allwinner V3s/S3L, but V3 comes with no co-packaged DDR (DDR3 is usually used externally), and S3L comes with co-packaged DDR3. Add support for Allwinner V3/S3 chips by add SoC names to original V3s choice, and allow to select DDR3. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* sunxi: DT: A64: update device tree filesSamuel Holland2020-11-1725-631/+2383
| | | | | | | | | | | | | Import updated device trees from Linux tag v5.9. This picks up new hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI files for the Pinebook and the Teres-I, since the ANX6345 bridge is now supported upstream. A couple of headers needed updates for recently-added hardware support. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* sunxi: board: Add PinePhone DT selection logicSamuel Holland2020-11-171-0/+7
| | | | | | | | | | | | There are two different publicly-released revisions of the PinePhone hardware, versions 1.1 and 1.2; and they need different device trees. Since some GPIO pins were rerouted, we can use that to distinguish between them. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge tag 'ti-v2021.01-rc3' of ↵Tom Rini2020-11-164-1/+259
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix Nokia RX-51 boot issues - Fix CONFIG_LOGLEVEL on K3 devices - Add phyBOARD REGOR support
| * ARM: am335x: Add phyBOARD REGOR supportParthiban Nallathambi2020-11-154-1/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060). CPU : AM335X-GP rev 2.1 Model: Phytec AM335x phyBOARD-REGOR DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 eth0: ethernet@4a100000 Working: - Eth0 - i2C - MMC/SD - NAND - UART - USB (host) Device trees were taken from Linux mainline: commit c4d6fe731176 ("Linux 5.9.0") Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'u-boot-amlogic-20201116' of ↵Tom Rini2020-11-168-97/+30
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Clock fix MMC driver for SM1 based platforms - sync SOC Ids from Linux 5.10-rc1 - fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
| * | ARM: dts: meson-sm1: add u-boot specific MMC controller compatibleNeil Armstrong2020-11-126-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to enable the Amlogic SM1 MMC controller fix, we need to add a u-boot specific MMC controller compatible. This adds a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi to use this for SM1 based boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | mmc: meson-gx: move arch header to local headerNeil Armstrong2020-11-121-92/+0
| | | | | | | | | | | | | | | | | | | | | Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h, remove the useless if/then and fix the meson_gx_mmc.c include. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * | ARM: mach-meson: update SoC IDsNeil Armstrong2020-11-121-1/+6
| |/ | | | | | | | | | | | | | | | | | | Update From Linux commits - 240051cb833b ("soc: amlogic: meson-gx-socinfo: Add A1 and A113L IDs") - 1d7c541b8a5b ("soc: amlogic: meson-gx-socinfo: Add S905X3 ID for VIM3L") - fdfc6997bd08 ("soc: amlogic: meson-gx-socinfo: Fix S905D3 ID for VIM3L") - d16d0481e6ba ("soc: amlogic: meson-gx-socinfo: Fix S905X3 and S905D3 ID's") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | rockchip: Enable BINMAN for boards enable SPL_OPTEEKever Yang2020-11-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | Rockchip has many 32bit SoCs and some of them are support SPL_OPTEE now, only boards with SPL_OPTEE support can fit BINMAN well, other boards will fail at initr_binman() in U-Boot proper after below patch, eg. rv1108 board. 83187546ae binman: Support multiple images in the library Fixes: 79030a4861 ("rockchip: Add Single boot image (with binman, pad_cat)") Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | rockchip: rockpro64: fix boot from SPI flash on spi1Hugh Cole-Baker2020-11-131-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") added an alias spi1 referring to spi@ff1d0000, however there was already an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and having both aliases present broke booting from SPI flash for this board. Remove the spi0 alias, set the default bus for SPI flash to 1, and enable support for numbered aliases in SPL so that it uses the same bus numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash on the rockpro64 board. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by: Simon Glass <sjg@chromium.org> Fixes: c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | video: rockchip: Restrict EDP, VOP, MIPI files to GPL-2.0Alper Nebi Yasak2020-11-132-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files have a lot of code in common with their counterparts in coreboot, especially in their earlier revisions: U-Boot | coreboot --------------------------------------|-------------------------------------------- drivers/video/rockchip/: | src/soc/rockchip/: - rk_edp.c (GPL-2.0+) | - common/edp.c (GPL-2.0-only) " | - rk3288/display.c (GPL-2.0-only) " | - rk3399/display.c (GPL-2.0-only) - rk_hdmi.h (GPL-2.0+) | (none) - rk_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3288_hdmi.c (GPL-2.0+) | - rk3288/hdmi.c (GPL-2.0-or-later) - rk3399_hdmi.c (GPL-2.0+) | (none) - rk_mipi.h (GPL-2.0+) | (none) - rk_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3288_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk3399_mipi.c (GPL-2.0+) | - rk3399/mipi.c (GPL-2.0-only) - rk_lvds.c (GPL-2.0+) | (none) - rk_vop.h (GPL-2.0+) | (none) - rk_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3288_vop.c (GPL-2.0+) | - common/vop.c (GPL-2.0-only) - rk3399_vop.c (GPL-2.0+) | (none) | arch/arm/include/asm/arch-rockchip/: | src/soc/rockchip/*/include/soc/*: - edp_rk3288.h (GPL-2.0+) | - common/.../edp.h (GPL-2.0-only) " | - rk3288/.../display.h (GPL-2.0-only) " | - rk3399/.../display.h (GPL-2.0-only) - vop_rk3288.h (GPL-2.0+) | - common/.../vop.h (GPL-2.0-only) Restrict the licenses to match coreboot's so that changes from coreboot can be imported to U-Boot as necessary. HDMI files are already 2.0+ there and rk_lvds.c has no counterpart, so keep them as is. Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Eric Gao <eric.gao@rock-chips.com> Cc: Jacob Chen <jacob-chen@iotwrt.com> Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* x86: coral: Update smbios tables to latest definitionSimon Glass2020-11-101-6/+21
| | | | | | | | The accepted binding uses multiple nodes, one for each table type. Update coral accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Avoid using hardcoded number of variable range MTRRs in mtrr_commit()Bin Meng2020-11-101-1/+1
| | | | | | | | | | | | | | | Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"), the maximum number of variable range MTRRs was increased from 8 to 10. On the BayTrail platform there are only 8 variable range MTRRs. In mtrr_commit() it still uses MTRR_MAX_COUNT which caused a #GP during VESA video driver probe. It should have been updated to use dynamically probed number. This fixes the boot failure seen on Intel Minnow Max board. Fixes: 29d2d64ed55f ("x86: Add support for more than 8 MTRRs") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dmWIP/06Nov2020Tom Rini2020-11-066-6/+58
|\ | | | | | | | | | | | | patman status subcommand to collect tags from Patchwork patman showing email replies from Patchwork sandbox poweroff command minor fixes in binman, tests
| * sandbox: implement resetHeinrich Schuchardt2020-11-054-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up to now the sandbox would shutdown upon a cold reset request. Instead it should be reset. In our coding we use static variables like LIST_HEAD(efi_obj_list). A reset can occur at any time, e.g. via an UEFI binary calling the reset service. The only safe way to return to an initial state is to relaunch the U-Boot binary. The reset implementation uses execv() to relaunch U-Boot. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: use O_CLOEXEC in os_open()Heinrich Schuchardt2020-11-051-0/+5
| | | | | | | | | | | | | | | | During a cold reset execv() is used to relaunch the U-Boot binary. We must ensure that all files are closed in this case. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: enable poweroff commandHeinrich Schuchardt2020-11-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The command to shut down a device is 'poweroff'. It is a deficit of the sandbox that it does not support resetting yet but shuts down upong seeing the 'reset' command. Once the sandbox properly supports reset we need the 'poweroff' command to leave the sandbox. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sandbox: eth-raw: do not close the console inputHeinrich Schuchardt2020-11-052-5/+8
| | | | | | | | | | | | | | | | | | | | When the sandbox eth-raw device host_lo is removed this leads to closing the console input. Do not call close(0). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-11-0662-144/+783
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Add a new SMBIOS parser and enable it when booting from coreboot - Fix up various driver names to avoid dtoc warnings - Fully enable ACPI support on Google Chromebook Coral - Add a way to set SMBIOS properties using the devicetree - Update existing boards to use devicetree for SMBIOS using a new default sysinfo driver
| * | x86: Provide default SMBIOS manufacturer/productSimon Glass2020-11-0616-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to be passed through the C preprocessor. Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: reword the commit message a little bit] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: galileo: Use devicetree for SMBIOS settingsSimon Glass2020-11-061-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | arm64: mvebu: Use devicetree for SMBIOS settings on uDPUSimon Glass2020-11-061-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | odroid-c2: Use devicetree for SMBIOS settingsSimon Glass2020-11-061-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULXSimon Glass2020-11-061-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | rockchip: Use devicetree for SMBIOS settingsSimon Glass2020-11-064-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | board: Rename uclass to sysinfoSimon Glass2020-11-062-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uclass is intended to provide a way to obtain information about a U-Boot board. But the concept of a U-Boot 'board' is the whole system, not just one circuit board, meaning that 'board' is something of a misnomer for this uclass. In addition, the name 'board' is a bit overused in U-Boot and we want to use the same uclass to provide SMBIOS information. The obvious name is 'system' but that is so vague as to be meaningless. Use 'sysinfo' instead, since this uclass is aimed at providing information on the system. Rename everything accordingly. Note: Due to the patch delta caused by the symbol renames, this patch shows some renamed files as being deleted in one place and created in another. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: zimage: Quieten down the zimage boot processSimon Glass2020-11-061-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Much of the output is not very useful. The bootm command is quite a bit quieter. Convert some output to use log_debug(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| * | x86: zimage: Sanity-check the kernel version before printing itSimon Glass2020-11-061-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With Chrome OS the kernel setup block is stored in a separate place from the kernel, so it is not possible to access the kernel version string. At present, garbage is printed. Add a sanity check to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: zimage: Add a little more loggingSimon Glass2020-11-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Add logging for each part of the boot process, using a new Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
| * | x86: fsp: Adjust calculations for MTRR range and DRAM topSimon Glass2020-11-061-13/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the top of available DRAM is the same as the top of the range of the low-memory MTRR. In fact, U-Boot is allowed to use memory up until the start of the FSP reserved memory. Use that value for low_end, since it makes more memory available. Keep the same calculation as before for mtrr_top, i.e. the top of reserved memory. A side-effect of this change is that the E820 tables have a single entry that extends from the bottom of the memory used by U-Boot to the bottom of the FSP reserved memory. This includes the bloblist, if ACPI tables are placed there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Don't show the UART address by defaultSimon Glass2020-11-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is useful when using Linux's earlycon since the MMIO address must be provided on some platforms, e.g.: earlycon=uart8250,mmio32,0xddffc000,115200n8 However this is only for debugging, so don't show it by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Include the TPMv1 table only if neededSimon Glass2020-11-061-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | This table is not needed if a v2 TPM is in use. Add a condition to avoid adding it when not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Silence some logging statementsSimon Glass2020-11-065-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | Quite a few log_info() calls are included in the x86 code which should use log_debug() instead. Convert them to reduce unwanted output. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: fsp: Convert fsp_dram to use log_debug()Simon Glass2020-11-061-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | Use log_debug() instead of debug() in this file, to enable the extra features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Set up Chrome OS to boot into developer modeSimon Glass2020-11-061-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | Set up a few fields necessarily to make Chrome OS boot without showing a firmware error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass2020-11-065-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Define the Chrome OS GNVS regionSimon Glass2020-11-061-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | It is not possible to boot Chrome OS properly without passing some basic information from U-Boot. This applies even if verified boot is not being used. Add a structure definition for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | acpi: Don't reset the tables with every new generationSimon Glass2020-11-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present if SSDT and DSDT code is created, only the latter is retained for examination by the 'acpi items' command. Fix this by only resetting the list when explicitly requested. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Put the generated code first in DSDTSimon Glass2020-11-061-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation for DSDT tables is not correct for the case where there is generated code, as the length ends up being incorrect. Also, we want the generated code to go first in the table. Rewrite this piece to correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Allow the SSDT to be emptySimon Glass2020-11-061-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | If there is nothing in the SSDT we should not include it in the tables. Update the implementation to check this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Show the interrupt pointer with 'irqinfo'Simon Glass2020-11-063-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | It is useful for this command to show the address of the interrupt table. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: nhlt: Fix a few bugs in the table generationSimon Glass2020-11-061-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | At present these tables do not have the correct header, and there is an occasional incorrect value due to uninited data. Fix these bugs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: nhlt: Correct output of bytes and 16-bit dataSimon Glass2020-11-061-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | At present these functions are incorrect. Fix them and add some logging and checking to avoid future problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Allow putting some tables in the bloblistSimon Glass2020-11-061-3/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present all tables are placed starting at address f0000 in memory, and can be up to 64KB in size. If the tables are very large, this may not provide enough space. Also if the tables point to other tables (such as console log or a ramoops area) then we must allocate other memory anyway. The bloblist is a nice place to put these tables since it is contiguous, which makes it easy to reserve this memory for linux using the 820 tables. Add an option to put some of the tables in the bloblist. For SMBIOS and ACPI, create suitable pointers from the f0000 region to the new location of the tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/project/uboot/patch/ 20201105062407.1.I8091ad931cbbb5e3b6f6ababdf3f8d5db0d17bb9@changeid/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Use if instead of #ifdef in write_tables()Simon Glass2020-11-051-19/+19
| | | | | | | | | | | | | | | | | | | | | Use if() to remove the extra build path in this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add SMBIOS info for CoralSimon Glass2020-11-051-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | This is required by Chrome OS so that the audio and other unibuild features work correctly. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: coral: Drop the duplicate PCIe settingsSimon Glass2020-11-051-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | These settings are included twice. The second lot are correct, so drop the others. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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