summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
* xtensa: use asm-generic/atomic.hChris Packham2018-09-251-43/+1
| | | | | | | Make use of asm-generic/atomic.h. Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Max Filippov <jcmvbkbc@gmail.com>
* mips: use asm-generic/atomic.hChris Packham2018-09-251-43/+1
| | | | | | Make use of asm-generic/atomic.h. Signed-off-by: Chris Packham <judge.packham@gmail.com>
* ARM: use asm-generic/atomic.hChris Packham2018-09-251-146/+1
| | | | | | | Make use of asm-generic/atomic.h retaining the smp_mb_... definitions. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: omap_hsmmc: Fix pbias for omap3_logic to enable CD pinAdam Ford2018-09-251-0/+1
| | | | | | | | | The MMC card detect pin is connected to gpio127 on omap3_logic. When setting up the pbias register for MMC, let's also enable gpio_127 for the card detect. As part of the package deal, gpio_126 and gpio_129 are also enabled. Signed-off-by: Adam Ford <aford173@gmail.com>
* arm: spear: fix enabling of SSP2 clockQuentin Schulz2018-09-251-1/+1
| | | | | | | | The SSP2 clock is at bit 6 in the register, so the value is 0x40 unlike the current 0x70 which enables the clock of UART2, SSP1 and SSP2. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Stefan Roese <sr@denx.de>
* arm: spear: enable SSP1, 2 and 3 clocks when SPI controller driver is builtQuentin Schulz2018-09-252-0/+5
| | | | | | | SPI controllers SSP1, 2 and 3 require to enable their respective clocks. Let's enable them only when the SPI controller driver is built. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
* ARM: dts: stm32mp1: Add EHCI support for stm32mp157c-ev1 boardPatrice Chotard2018-09-251-0/+7
| | | | | | Add DT nodes to enable EHCI support Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* ARM: dts: stm32mp1: Add usb gadget support for stm32mp157c-ev1 boardPatrice Chotard2018-09-254-0/+55
| | | | | | Add DT nodes to enable DWC2 gadget support Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* mips: mt7628a.dtsi: Add SPI clock-frequency propertyStefan Roese2018-09-231-0/+2
| | | | | | | | This patch adds the clock-frequency property to the SPI controller DT node. It will be used by the SPI driver to calculate the baud rate. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: mt76xx: Add sysreset supportStefan Roese2018-09-232-0/+8
| | | | | | | | This patch adds the necessary sysreset DT node and enables the required drivers via Kconfig. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: Add Gardena Smart-Gateway board supportStefan Roese2018-09-232-0/+63
| | | | | | | | | | | | | | | The Gardena Smart-Gateway boards have a MT7688 SoC with 128 MiB of RAM and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND storage. This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese <sr@denx.de> [fixed and regenerated defconfig files] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: Add LinkIt Smart 7688 supportStefan Roese2018-09-232-0/+59
| | | | | | | | | | | | | | | The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM and 32 MiB of flash (SPI NOR). This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: Stefan Roese <sr@denx.de> [fixed and regenerated defconfig files] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: Add basic MediaTek MT7620/88 supportStefan Roese2018-09-229-0/+1004
| | | | | | | | | | | | | | | This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of the code is copied from the MediaTek GitHub repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git The mt7628a.dtsi file is imported from Linux v4.17. Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway both based on the MT7688 will be added in further patches. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: Add arch/mips/include/asm/atomic.hStefan Roese2018-09-221-0/+54
| | | | | | | | This is needed for the UBIFS support. The file is a copy of arch/xtensa/include/asm/atomic.h Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODEDaniel Schwierzeck2018-09-221-5/+1
| | | | | | | | Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: cache: make index base address configurableDaniel Schwierzeck2018-09-222-10/+20
| | | | | | | | The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS system needs to have a different address (e.g. in SRAM or ScratchPad RAM). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: cache: optimise changing of k0 CCA modeDaniel Schwierzeck2018-09-221-22/+32
| | | | | | | | Changing the Cache Coherency Algorithm (CCA) for kernel mode requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1 before changing the CCA mode. Jump back to KSEG0 afterwards. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: cache: reimplement dcache_[status, enable, disable]Daniel Schwierzeck2018-09-222-46/+20
| | | | | | | | | | | Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when this is required for booting an OS. Reenabling caches is much harder to implement if an optional coherency manager must be supported. As there is no real use-case anyway, dcache_enable is implemented with an error message. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: start.S: make boot config at offset 0x10 configurableDaniel Schwierzeck2018-09-222-16/+28
| | | | | | | | | | | | Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* dt: bcm6838: add pinctrlPhilippe Reynes2018-09-221-0/+12
| | | | | | Add pinctrl node and related syscon node for broadcom bcm6838 SoC. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
* Merge git://git.denx.de/u-boot-imxTom Rini2018-09-192-1/+2
|\ | | | | | | | | - changes in pico-* boards - fix imx6ull pinmux
| * Merge branch 'master' of git://git.denx.de/u-boot into masterStefano Babic2018-09-1818-200/+525
| |\ | | | | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | imx: imx6ull: fix pinmux input_val for uart5 rx pinHeiko Schocher2018-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | just try to bring up an imx6ull board with console on uart5 and found, that input_val for pin MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX is 7 and not 5 on imx6ull. With this patch rx works now. Signed-off-by: Heiko Schocher <hs@denx.de>
| * | pico-imx6ul: Convert to SPLFabio Estevam2018-09-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two versions of imx6ul pico SOMs: one with 256MB and another one with 512MB of RAM. Convert to SPL so that both versions can be supported. This patch doesn't rework the clock initialization to avoid changing the behavior in this same patch, so it will be cleaned up in future. Currently only the 256MB is tested/supported. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Fabio Berton <fabio.berton@ossystems.com.br> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* | | Merge git://git.denx.de/u-boot-marvellTom Rini2018-09-195-28/+44
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Multiples updates to the turris boards / platform - Changes / enhancements to the Marvell PHY drivers, mainly to support the turris platform - Many fixes and enhancements to the pxa3xx NAND driver - Fixes for the UART boot mode in kwboot - Misc minor changes to other 32bit and 64bit boards
| * | | board: turris_mox: Fixup U-Boot's device tree if PCIe connectedMarek Behún2018-09-191-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If PCIe Mox module is connected we want to have PCIe node enabled in U-Boot's device tree. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | dts: mvebu: mcbin: drop redundant SD slot nodeBaruch Siach2018-09-191-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 61dccf73d302 (dts: mvebu: a80x0: Enable SD/eMMC interfaces) added a redundant DT node for SD card slot. Drop it. Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | arch/arm/dts: Update Turris Mox device treeMarek Behún2018-09-191-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove smi_pins definition since it is already in armada-37xx.dtsi. Add assigned-clocks definitions to spi0. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ARM: mach-mvebu: handle fall-back to UART bootChris Packham2018-09-192-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootROM in the Armada-38x (and similar) SoC has two modes for UART boot. The first is when the normal boot media is blank (or otherwise missing the kwb header). The second is when the boot sequence has been interrupted with the magic byte sequence on the UART lines. In the first mode the bootROM routine and error code register will indicate that there was an error booting from the configured media in bits 7:0. In the second mode there is no error to indicate but the boot source is provided via bits 31:28. Handle both situations so that kwboot can be used for both boot strapping a blank board and for intercepting a regular boot sequence. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | Revert "arm: mvebu: fix boot from UART when in fallback mode"Chris Packham2018-09-192-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e83e2b390038c9075642cb243a6292241beb8d73. This prevents kwboot from overriding the hardware strapped boot source. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | arm64: mvebu: armada-8k: support environment in SD/eMMCBaruch Siach2018-09-191-0/+24
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect the SD/eMMC boot device at run-time. Load the environment from the boot deice, as well as save to it. Leave the environment offset the same as in the SPI flash. Make SD/eMMC 0 the default environment device when the boot device is not detected. Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge git://git.denx.de/u-boot-dmTom Rini2018-09-1816-5/+145
|\ \ \ | |/ / |/| | | | | | | | | | | | | | - MPC83xx device tree additions (CPU and RAM) - Fix sandbox build error - Sync bitrev with Linux - Various ofnode/DT improvements
| * | misc: Add MPC83xx serdes driverMario Six2018-09-182-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * | cpu: Add MPC83xx CPU driverMario Six2018-09-183-0/+6
| | | | | | | | | | | | | | | | | | Add a CPU driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * | test: Add tests for CPU uclassMario Six2018-09-181-0/+12
| | | | | | | | | | | | | | | | | | Add a sandbox CPU driver, and some tests for the CPU uclass. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * | timer: Add MPC83xx timer driverMario Six2018-09-183-3/+10
| | | | | | | | | | | | | | | | | | Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * | clk: Add MPC83xx clock driverMario Six2018-09-184-1/+83
| | | | | | | | | | | | | | | | | | Add a clock driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * | mpc83xx: Add sysreset driverMario Six2018-09-181-1/+2
| | | | | | | | | | | | | | | | | | | | | Add a sysreset driver for the MPC83xx platform. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * | powerpc: Add read*_*/write*_* macrosMario Six2018-09-181-0/+18
| | | | | | | | | | | | | | | | | | | | | Define the read*_*/write*_* macros for the PowerPC platform to be able to use the macros in wait_bit.h. Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * | ram: Add driver for MPC83xxMario Six2018-09-181-0/+4
| | | | | | | | | | | | | | | | | | | | | Add a RAM driver for the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
| * | sandbox: Enable bitrev library buildBin Meng2018-09-181-0/+1
| | | | | | | | | | | | | | | | | | | | | Imply CONFIG_BITREVERSE for Sandbox. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Build with -fPICAndy Shevchenko2018-09-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandbox is not a real bootloader and it does require a position independent code to be supported. Thus, build it with -fPIC explicitly. Fixes: 16940f720f9b ("Makefile: Don't generate position independent code") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reported-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | | Merge git://git.denx.de/u-boot-x86Tom Rini2018-09-176-1/+293
|\ \ \ | |/ / |/| |
| * | x86: cpu: add docstring to scu_ipc_command()Georgii Staroselskii2018-09-171-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | These comments were copied from the Linux kernel driver in drivers/platform/x86/intel_scu_ipc.c Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: tangier: acpi: add I2C6 nodeGeorgii Staroselskii2018-09-171-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have I2C#6 working, it's time to add a corresponsing ACPI binding. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: dts: edison: configure I2C#6 pinsGeorgii Staroselskii2018-09-171-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have the pinctrl driver for Merrifield in place we can make use of it and set I2C#6 pins appropriately. Initial configuration came from the firmware. Which quite likely has been used in the phones, where that is not part of Atom peripheral, is in use. Thus we need to override the leftover. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: tangier: pinmux: add API to configure protected pinsGeorgii Staroselskii2018-09-172-1/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This API is going to be used to configure some pins that are protected for simple modification. It's not a comprehensive pinctrl driver but can be turned into one when we need this in the future. Now it is planned to be used only in one place. So that's why I decided not to pollute the codebase with a full-blown pinctrl-merrifield nobody will use. This driver reads corresponding fields in DT and configures pins accordingly. The "protected" flag is used to distinguish configuration of SCU-owned pins from the ordinary ones. The code has been adapted from Linux work done by Andy Shevchenko in pinctrl-merrfifield.c Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix build warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: cpu: introduce scu_ipc_raw_command()Georgii Staroselskii2018-09-172-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This interface will be used to configure properly some pins on Merrifield that are shared with SCU. scu_ipc_raw_command() writes SPTR and DPTR registers before sending a command to SCU. This code has been ported from Linux work done by Andy Shevchenko. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-coldfireTom Rini2018-09-165-15/+36
|\ \ \
| * | | m68k: ColdFire mcf5441x, add eSDHC supportAngelo Dureghello2018-09-163-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds mcf5441x eSDHC support for the mcf5441x family. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
View Lorry Controller Status