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* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/05Feb2020Tom Rini2020-02-058-32/+112
|\ | | | | | | | | - Bug fixes on ls1012a, ls1021a, ls1028ardb platforms Integrate fspi for ls1028a, add DM-I2C support, update secure boot header offset
| * dm: arm64: ls1012a: add i2c DM supportBiwen Li2020-02-042-2/+3
| | | | | | | | | | | | | | | | This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1012A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: fsl-layerscape: spl: fix build error when DM_I2C is enabledBiwen Li2020-02-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix below SPL build error when DM_I2C is enabled, - arch/arm/cpu/armv8/built-in.o: In function `board_init_f: arch/arm/cpu/armv8/fsl-layerscape/spl.c:74: undefined reference to `i2c_init_all' arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:(.text.board_init_f+0x30): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `i2c_init_all' make[2]: *** [spl/u-boot-spl] Error 1 make[1]: *** [spl/u-boot-spl] Error 2 make: *** [sub-make] Error 2 arch/arm/cpu/armv8/fsl-layerscape/spl.c: In function 'board_init_f': arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:2: warning: implicit declaration of function 'i2c_init_all'; did you mean 'misc_init_r'? [-Wimplicit-function-declaration]` Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: lx2160a: Add FSPI node propertiesKuldeep Singh2020-02-042-1/+38
| | | | | | | | | | | | | | | | Align flexspi node properties with linux device-tree properties Tested on LX2160A-RDB Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: ls1028a: Add FSPI node propertiesKuldeep Singh2020-02-042-0/+31
| | | | | | | | | | | | | | | | Align flexspi node properties with linux device-tree properties Tested on LS1028A-RDB Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: ls1028a: fix interrupt propertiesMichael Walle2020-02-041-24/+31
| | | | | | | | | | | | | | | | | | | | | | Sync the interrupt properties with the ones from Linux. Also use the constants provided by the dt-bindings header. Please note, that there are actual changes/fixes in the irq flags. U-Boot won't use the interrupt properties anyway. It's just to be consistent with the Linux device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: ls1028a: use the new flexspi driverMichael Walle2020-02-041-6/+8
| | | | | | | | | | | | | | | | Also align the fspi node with the kernel one. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | Merge tag 'rpi-next-2020.04' of ↵Tom Rini2020-02-051-3/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - DFU support file operations lager then the default max size - add dfu support to dwc2 for bcm2835 - enable DFU for RPi4 - Fix RPi4 memory map to include the genet device - add driver for the genet ethernet device - enable network support in RPi4 config
| * | rpi4: Update memory map to accommodate scb devicesAmit Singh Tomar2020-01-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the devices(for instance, pcie and gnet controller) sitting on SCB bus falls behind/below the memory range that we currenty have. This patch updates the memory range to map those devices correctly. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86WIP/04Feb2020Tom Rini2020-02-0413-46/+79
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Various minor fixes for x86 - Switch to ACPI mode on Intel edison - Support run-time configuration for NS16550 driver - Update coreboot and slimbootloader serial drivers to use NS16550 run-time configuration - ICH SPI driver fixes to hardware sequencing erase case - Move ITSS from Apollo Lake to a more generic location - Intel GPIO driver bug fixes - Move to vs2017-win2016 platform build host for Azure pipelines
| * | | x86: itss: Remove apl-prefixWolfgang Wallner2020-02-042-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so remove the apl-prefix of the implemented functions/structures/... Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: itss: Add a Kconfig option to enable/disable ITSS driverWolfgang Wallner2020-02-043-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Kconfig option to support enabling/disabling the inclusion of the ITSS driver depending on the platform. Atuomatically select the ITSS driver when building for Apollo Lake. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232761/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: Move itss.c from Apollo Lake to a more generic locationWolfgang Wallner2020-02-043-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so move it to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: conditionally build itss.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: Move itss.h from Apollo Lake to the generic x86 include directoryWolfgang Wallner2020-02-042-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code in this file is not specific to Apollo Lake. According to coreboot sources (where this code comes from), it is common to at least: * Apollo Lake * Cannon Lake * Ice Lake * Skylake Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: apl: Add the term "Interrupt Timer Subsystem" to ITSS filesWolfgang Wallner2020-02-042-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ITSS stands for "Interrupt Timer Subsystem", so add that term to the description of the relevant files. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: limit the fs segment to the pointer sizeMasahiro Yamada2020-02-041-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fs segment is only used to get the global data pointer. If it is accessed beyond sizeof(new_gd->arch.gd_addr), it is a bug. To specify the byte-granule limit size, drop the G bit, so the flag field is 0x8093 instead of 0xc093, and set the limit field to sizeof(new_gd->arch.gd_addr) - 1. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed the comments about FS segement] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: use invd instead of wbinvd in real mode start codeMasahiro Yamada2020-02-042-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I do not know why the boot code immediately after the system reset should write-back the cache content. I think the cache invalidation should be enough. I tested this commit with qemu-x86_defconfig, and it worked for me. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: serial: Use NS16550_DYNAMIC in Slim BootloaderPark, Aiden2020-02-041-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Slim Bootloader provides serial port info in its HOB to support both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32 or SYS_NS16550_PORT_MAPPED in U-Boot. To support both serial port configurations dynamically at runtime, Slim Bootloader serial driver leverages NS16550_DYNAMIC. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove the obsolete comments for data->type] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: Move coreboot over to use the coreboot UARTSimon Glass2020-02-041-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use this UART to improve the compatibility of U-Boot when used as a coreboot payload. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: Update coreboot serial table structSimon Glass2020-02-041-0/+19
| | |/ | |/| | | | | | | | | | | | | | | | | | | Since mid 2016, coreboot has additional fields in the serial struct that it passes down to U-Boot. Add these so we are in sync. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | arm: dts: k3-j721e-main: Add Support for gpio0Faiz Abbas2020-02-041-0/+22
| | | | | | | | | | | | | | | | | | | | | Add the main_gpio0 node. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | arm: dts: k3-j721e-common-proc-board: Enable I2C expander for SPLVignesh Raghavendra2020-02-042-0/+39
| | | | | | | | | | | | | | | | | | | | | IO expanders are required to power cycle SD card. So enable the same Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | arm: dts: k3-j721e-common-proc-board: Add I2C GPIO expanderVignesh Raghavendra2020-02-041-0/+27
| | | | | | | | | | | | | | | | | | | | | Add I2C GPIO expander required to power cycle MMC/SD Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | arm: dts: k3-j721e: Add I2C nodesVignesh Raghavendra2020-02-043-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | J721e SoC has 2 I2C instances in MCU domain and 7 I2C instances in main domain. Add DT nodes for the same Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | arm: dts: k3-j721e-common-proc-board: Enable USB0 in peripheral modeVignesh Raghavendra2020-02-041-0/+18
| | | | | | | | | | | | | | | | | | | | | Enable USB0 in peripheral mode so that it be used for DFU Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | arm: mach-k3: sysfw-loader: Add support to download SYSFW via DFUVignesh Raghavendra2020-02-041-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to download SYSFW into internal RAM via DFU in DFU boot mode. Prepare a DFU config entity entry dynamically using buffer address allocated for SYSFW and start DFU gadget to get SYSFW. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | arm: mach-k3: j721e: Rename BOOT_DEVICE_USB to BOOT_DEVICE_DFUVignesh Raghavendra2020-02-041-1/+1
|/ / | | | | | | | | | | | | | | | | | | J721e does not support USB Host MSC boot, but only supports DFU boot. Since BOOT_DEVICE_USB is often used for host boot mode and BOOT_DEVICE_DFU is used for DFU boot, rename BOOT_DEVICE_USB macro to BOOT_DEVICE_DFU Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Merge tag 'u-boot-rockchip-20200130' of ↵WIP/01Feb2020Tom Rini2020-02-0126-741/+1214
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Support redundant boot for rk3399 - Support binman for rockchip platform - Update ram driver and add ddr4 support for rk3328
| * | rockchip: rk3308: add alias for emmc/sdmmcKever Yang2020-01-301-0/+7
| | | | | | | | | | | | | | | | | | | | | Add alias for mmc/sdmmc so that we can have a fix mmc number for emmc. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | ram: rk3328: update lpddr3 settingYouMin Chen2020-01-301-4/+4
| | | | | | | | | | | | | | | | | | | | | update lpddr3 setting for fix init fail about "col error". Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | ram: rk3328: add support ddr4 initYouMin Chen2020-01-301-0/+216
| | | | | | | | | | | | | | | | | | | | | Add rk3328-sdram-ddr4-666.dtsi for support ddr4 init. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: Add Single boot image (with binman, pad_cat)Jagan Teki2020-01-305-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All rockchip platforms support TPL or SPL-based bootloader in mainline with U-Boot proper as final stage. For each stage we need to burn the image on to flash with respective offsets. This patch creates a single boot image component using - binman, for arm32 rockchip platforms - pad_cat, for arm64 rockchip platforms. This would help users to get rid of burning different boot stage images. The new image called 'u-boot-rockchip.bin' which can burn into flash like: ₹ sudo dd if=u-boot-rockchip.bin of=/dev/sda seek=64 This would support all rockchip platforms, except rk3128 since it doesn't support for SPL yet. Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Cc: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: dts: rk3188: Add rk3188-u-boot.dtsiJagan Teki2020-01-302-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add U-Boot specific dtsi file for rk3188 SoC. This would help to add U-Boot specific dts nodes, properties which are common across rk3188. Right now, the file is empty, will add required changes in future patches. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: dts: rk3036: Add rk3036-u-boot.dtsiJagan Teki2020-01-302-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add U-Boot specific dtsi file for rk3036 SoC. This would help to add U-Boot specific dts nodes, properties which are common across rk3036. Right now, the file is empty, will add required changes in future patches. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3399: Add bootcount supportJagan Teki2020-01-302-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bootcount support for Rockchip rk3399. The bootcount value is preserved in PMU_SYS_REG0 register, this would help to support redundent boot. Once the redundant boot triggers, the altboot command will look for extlinux-rollback.conf on particular bootable partition which supposed to be a recovery partition where redundant boot required. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | rockchip: Add common reset causeJagan Teki2020-01-304-52/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cpu reset cause in common cpu-info file. This would help to print the reset cause for various resets. Right now it support rk3288, rk3399. rest of rockchip platforms doesn't have reset cause support ye but this code is more feasible to extend the same. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | arm: rockchip: Add common cru.hJagan Teki2020-01-308-16/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | rockchip: Add cpu-infoJagan Teki2020-01-302-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cpu information for rockchip soc. This would help to print the SoC family number, with associated temparature, clock and reason for reset etc. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | rockpro-rk3399: Enable SPI FlashJagan Teki2020-01-301-0/+4
| | | | | | | | | | | | | | | | | | | | | Enable winbond SPI flash for ROC-PC-RK3399 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | roc-pc-rk3399: Enable SPI FlashJagan Teki2020-01-301-0/+4
| | | | | | | | | | | | | | | | | | | | | Enable winbond SPI flash for ROC-PC-RK3399 board. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: dts: Sync ROC-RK3399-PC changes from LinuxJagan Teki2020-01-302-670/+816
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync the ROC-RK3399-PC device tree changes from Linux with below commit details: commit <c36308abe4110e4db362d5e2ae3797834a7b1192> ("arm64: dts: rockchip: Enable MTD Flash on rk3399-roc-pc") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | Merge tag 'uniphier-v2020.04-2' of ↵WIP/31Jan2020Tom Rini2020-01-319-79/+10
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.04 (2nd) Denali NAND driver changes: - Set up more registers in denali-spl for SOCFPGA - Make clocks optional - Do not assert reset signals in the remove hook - associate SPARE_AREA_SKIP_BYTES with DT compatible - switch to UCLASS_MTD UniPhier platform changes: - fix a bug in dram_init() - specify loadaddr for "source" command
| * | ARM: uniphier: set gd->ram_base correctlyMasahiro Yamada2020-02-011-6/+1
| | | | | | | | | | | | | | | | | | | | | gd->ram_base is not set at all if the end address of the DRAM ch0 exceeds the 4GB limit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mtd: rawnand: denali_dt: use UCLASS_MTD instead of UCLASS_MISCMasahiro Yamada2020-02-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UCLASS_MTD is a better fit for NAND drivers. Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile drivers/mtd/mtd-uclass.c Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig of this platform enables NAND_DENALI_DT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * | ARM: uniphier: remove adhoc reset deassertion for the NAND controllerMasahiro Yamada2020-02-017-73/+8
| |/ | | | | | | | | | | | | Now that the reset controlling of the Denali NAND driver (denali_dt.c) works for this platform, remove the adhoc reset deassert code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-samsungTom Rini2020-01-283-2/+4
|\ \ | |/ |/| | | - Various exynos fixes
| * arm: exynos: Read default MMC device from XOM[7:5] pinsMarek Szyprowski2020-01-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | XOM pins provide information for iROM bootloader about the boot device. Those pins are mapped to lower bits of OP_MODE register (0x10000008), which is common for all Exynos SoC variants. Set the default MMC device id to reflect the boot device selected by XOM[7:5] pins (2 for the SD or 0 for the eMMC). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: dts: exynos: Use common alias for Odroid U3/X2 MMC2 (SD-card)Marek Szyprowski2020-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | Use MMC0 for eMMC and MMC2 for SD-card as other Exynos-based boards do. This allows to use common code to get MMC device id based on the XOM[7:5] pins. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: dts: exynos: Fix card-detect polarity for SD card on Odroid U3/X2Marek Szyprowski2020-01-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | Card detect line for SD-card on Odroid U3/X2 boards are active low, so add cd-inverted property to indicate this, as u-boot's GPIO driver doesn't support specifying line polarity. This restores S5P_SDHCI driver operation on Odroid U3/X2 boards. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: dts: exynos: Extend board descriptionMarek Szyprowski2020-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | u-boot uses the same DTS for the all Odroid XU3-based boards, so list them in the model description to let user know that those boards are supported. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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