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* Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchipTom Rini2019-05-3110-89/+1465
|\ | | | | | | | | | | | | - some fix for rk3399-puma; - rockchip script make_fit_atf.py cleanup - Enable TPL for rk3399 orangepi and nanopi4; - add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
| * rockchip: rk3399: Add Rock PI 4 supportJagan Teki2019-05-303-0/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Rock PI 4 board. Specification - Rockchip RK3399 - LPDDR4 - eMMC - SD card slot - RTL8211E 1Gbps - HDMI In/Out, DP, MIPI DSI/CSI - PCIe M.2 - USB 2.0, USB-3.0 - USB C Type Commit details of rk3399-rock-pi-4.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: add ROCK Pi 4 DTS support" (sha1: 1b5715c602fda7b812af0e190eddcce2812e5417) Signed-off-by: Akash Gajjar <akash@openedev.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: Add Rockpro64 board supportJagan Teki2019-05-303-0/+719
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Rockpro64 board. Specification - Rockchip RK3399 - 2/4GB Dual-Channel LPDDR3 - SD card slot - eMMC socket - 128Mb SPI Flash - Gigabit ethernet - PCIe 4X slot - WiFI/BT module socket - HDMI In/Out, DP, MIPI DSI/CSI, eDP - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 12V/2A Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2: "arm64: dts: rockchip: rockpro64 dts add usb regulator" (sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb) 'Akash' has sent an initial patch before, so I keep him as board maintainer and I'm co-maintainer based on our conversation. Signed-off-by: Akash Gajjar <akash@openedev.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: Add Nanopi NEO4 board supportJagan Teki2019-05-303-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Nanopi NEO4 board. Specification - Rockchip RK3399 - 1GB DDR3-1866 - SD card slot - eMMC Socket - RTL8211E 1Gbps - AP6212 WiFI/BT - HDMI In/Out, DP, MIPI CSI - USB 3.0, 2.0 - USB Type C power and data - GPIO expansion ports - DC 5V/3A Commit details of rk3399-nanopi-neo4.dts sync from Linux: "arm64: dts: rockchip: Add Nanopi NEO4 initial support" (sha1: 092470b537f19788d957aed12d835a179b606014) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: Cleanup of make_fit_atf.py.Christoph Muellner2019-05-301-89/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up make_fit_atf.py in the following way: * Fix all issues reported by pylint * Move copyright notice from file-to-generate to script * Fix of-by-one bugs in loadables property * Remove commented-out (dead) code. Besides the bugfix no intended changes. Tested on RK3399-Q7 with TF-A v2.1 as BL31. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: Add option to print on UART3.Christoph Muellner2019-05-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | The RK3399 SPL does not use a pinctrl driver to setup the UART pins. Instead it works based on config macros, which set the base address of the actual UART block. Currently the RK3399 SPL support UART0 and UART2. This patch adds UART3 in the same way as UART0. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: pinctrl: rk3399: Add support for UART3.Christoph Muellner2019-05-301-0/+4
| | | | | | | | | | | | | | | | This patch adds the missing GRF bit definitions for UART3 on the RK3399. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | ARM: meson-gx: Reset GXL/GXM to external PHY when not using internal PHYNeil Armstrong2019-05-311-5/+12
| | | | | | | | | | | | | | | | When using External PHY, reset the mux to use the external PHY in case U-Boot was chainloaded from a misconfigured bootloader. Fixes: 33e3378091 ("ARM: meson: rework soc arch file to prepare for new SoC") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | ARM: dts: Add missing DT for Meson G12A supportNeil Armstrong2019-05-312-0/+279
| | | | | | | | | | | | | | | | The following DT nodes in the process on review for Linux 5.3, until Linux 5.3 is tagged, add the missing DT nodes in u-boot specific DTSI files that will be dropped when the v5.3-rc1 DT is synced again. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | ARM: dts: sync Amlogic G12A DT with Linux 5.2-rc1Neil Armstrong2019-05-312-0/+612
|/ | | | | | Sync from Linux commit a188339ca5a3 ("Linux 5.2-rc1") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2019-05-294-1/+683
|\ | | | | | | - Audio support
| * tegra: sound: Add an I2S driverSimon Glass2019-05-241-0/+206
| | | | | | | | | | | | | | | | | | | | Add a driver which supports transmitting digital sound to an audio codec. This uses fixed parameters as a device-tree binding is not currently defined. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: sound: Add an audio hub driverSimon Glass2019-05-241-0/+475
| | | | | | | | | | | | | | | | | | Add a driver for the audio hub. This is modelled as a misc device which supports writing audio data from I2S. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: Add a delay in clock_start_periph_pll()Simon Glass2019-05-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | This function enables a peripheral clock and then immediately sets its divider. Add a delay to allow the clock to settle first. This matches the delay in other places which do a similar thing. Without this, the I2S device on Nyan does not init properly. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * tegra: Correct tegra124 clock nameSimon Glass2019-05-241-1/+1
| | | | | | | | | | | | | | | | The first clock type appears to have and incorrect setting for out of the mux outputs. It should be CLK_M, not OSC. Fix it and its only user. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | mcx: remove boardBartosz Golaszewski2019-05-282-8/+0
| | | | | | | | | | | | | | | | | | This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* | twister: remove boardBartosz Golaszewski2019-05-282-7/+0
| | | | | | | | | | | | | | | | | | | | This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | mt_ventoux: remove boardBartosz Golaszewski2019-05-282-7/+0
| | | | | | | | | | | | | | | | | | | | This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | cm_t3517: remove boardBartosz Golaszewski2019-05-282-8/+0
| | | | | | | | | | | | | | | | | | This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* | ipam390: remove boardBartosz Golaszewski2019-05-281-7/+0
| | | | | | | | | | | | | | | | | | | | This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Heiko Schocher <hs@denx.de>
* | eco5pk: remove boardBartosz Golaszewski2019-05-281-5/+0
| | | | | | | | | | | | | | | | | | This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* | ea20: remove boardBartosz Golaszewski2019-05-282-8/+0
| | | | | | | | | | | | | | | | | | | | This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | calimain: remove boardBartosz Golaszewski2019-05-282-6/+0
| | | | | | | | | | | | | | | | | | This board still doesn't select CONFIG_DM and seems to be umaintained. As it makes progress on modernizing several DaVinci drivers more difficult and the maintainer has not expressed interest in updating it, this patch proposes to remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-05-262-0/+84
|\ \ | | | | | | | | | | | | | | | - Gen3 PCIe driver + enablement on Salvator-X platforms. - Gen3 recovery SPL used to reload ATF/OpTee/U-Boot instead of minimon. - SDHI HS400 fixes ported from latest BSP and datasheet.
| * | ARM: rmobile: Add recovery SPL for R-Car Gen3Marek Vasut2019-05-212-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Build an SPL which can be started via SCIF download mode on R-Car Gen3 and allows loading and executing U-Boot uImage with the next stage code. This is also useful for starting e.g. ATF BL2, which inits the hardware and returns to the U-Boot SPL, which can then load e.g. U-Boot proper. The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL while the payload, e.g. ATF BL2, executes, so there is no problem here. However, E3 and D3 have much less SRAM, hence the loader uses a trick where it copies itself beyond the area used by BL2 and executes from there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS, stack and malloc area, so the later two are placed at +0x4000 offset from start of SRAM, another area not used by ATF BL2. To make things even more complicated, the SCIF loader cannot load to the upper 32kiB of the SRAM directly, hence the copying approach. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-05-265-61/+56
|\ \ \ | | | | | | | | | | | | - SoCFPGA PL310 cleanup + A10 fix, A10 DT cleanup, DW GPIO fix.
| * | | Arm: dts: socfpga: Remove invalid property from chose nodeTien Fong Chee2019-05-241-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Finding bitstream from cff-file is no longer valid after bitstream is built into FIT image and loaded by generic firmware loader. Remove cff-file as this is legacy implementation from A10 downstream. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Clear PL310 early in SPLMarek Vasut2019-05-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On SoCFPGA A10 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Pull PL310 clearing into common codeMarek Vasut2019-05-243-57/+55
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull the PL310 clearing code into common code, so it can be reused by Arria10. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | | Merge tag 'mips-pull-2019-05-24' of git://git.denx.de/u-boot-mipsTom Rini2019-05-252-16/+1
|\ \ \ | | | | | | | | | | | | | | | | - mtmips: network stability fixes for gardena-smart-gateway - mtmips: enable CONFIG_USE_PREBOOT and CONFIG_CMD_WDT
| * | | mips: mt76xx: Remove cache workaround and select SYS_MALLOC_CLEAR_ON_INITStefan Roese2019-05-242-16/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 06985289d452 ("watchdog: Implement generic watchdog_reset() version") the init sequence has changed in arch_misc_init(), resulting in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena). When this happens, the first (or sometimes later ones as well) TFTP command hangs and does not complete correctly. This leads to the assumption that the d-cache is not in a clean state once the ethernet driver is called (d-cache is used here for the buffers). The old work- around with the cache flush somehow does not work any more now with the new code change. To fix this issue, this patch now removes the old workaround and selects CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the complete malloc area is initialized with zeros (cache lines are touched). Testing has shown that this also fixes the issue on the MT7688 boards. Signed-off-by: Stefan Roese <sr@denx.de> Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | Merge tag 'u-boot-stm32-20190523' of https://github.com/pchotard/u-bootTom Rini2019-05-249-22/+72
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add various STM32MP1 fixes for serial, env, clk, board, i2c ... - Add STM32MP1 DDR driver update: These update introduce the DDR interactive mode described in: https://wiki.st.com/stm32mpu/index.php/U-Boot_SPL:_DDR_interactive_mode This mode is used by the CubeMX: DDR tuning tool. https://wiki.st.com/stm32mpu/index.php/STM32CubeMX The DDR interactive mode is NOT activated by default because it increase the SPL size and slow down the boot time (200ms wait added).
| * | | stm32mp1: ram: add support for LPDDR2/LPDDR3Patrick Delaunay2019-05-231-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Manage power supply configuration for board using stpmic1 with LPDDR2 or with LPDDR3: + VDD_DDR1 = 1.8V with BUCK3 (bypass if possible) + VDD_DDR2 = 1.2V with BUCK2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | ARM: dts: stm32mp1: DDR config v1.44Patrick Delaunay2019-05-232-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update DDR configuration with the latest update: - PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte lane 2/3 in 16bit - fix LPDDR2/3 timing_calc to step RL/WL in relaxed timings mode - remove LPDDR3 RL3 (optional) support vs MR0[7] because MR0[7] can't be read instead always apply worse RL/WL for LPDDR3 when freq < 166MHz) - change MR3 to 48ohm drive for LPDDR2/3 - change default ZPROG[7:4] = 0x1 for LPDDR2/3 , '0' is not allowed even when ODT not used - use DQSTRN for LPDDR2/3 (it was not set in PIR) - LPDDR3: set dqsge/dwsgx gate extension to 2,2 like LPDDR2 -DDRCTRL.dfitmg0: + for LPDDR3 tphy_wrlat = WL (as LPDDR2) + improvement for relaxed mode vs RL/Wl at corner case. For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3 and correction to MR2 accordingly - DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40, for LTDC. - DDR_PCFGWQOS0_0: change vpr level from 11 to 12 in order to include the CPU on the variable priority queue. - DDR_SCHED: fix to consider 13 levels (13 levels - 1 = 0xC) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: ram: change ddr speed to kHzPatrick Delaunay2019-05-232-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Allow fractional support in DDR tools. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: add bootstage supportPatrick Delaunay2019-05-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the needed configurations for bootstage and activate bootstage command. BOOTSTAGE_REPORT is not activated by default. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | armv7: timer: init timer with bootstagePatrick Delaunay2019-05-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In initf_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us() before timer_init(); that cause crash for stm32mp1. This patch solve the issue without changing the initialization sequence. See also commit 97d20f69f53e ("Enable CONFIG_TIMER_EARLY with bootstage") for other solution when DM is activated for TIMER. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: add bootcount supportPatrick Delaunay2019-05-232-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Activate bootcount and use TAMP register to store the count value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: psci: add synchronization with ROM codePatrick Delaunay2019-05-231-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER to synchronize the core1 boot sequence requested by core0 in psci_cpu_on(): - a initial interruption is needed in ROM code after RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off) - the ROM code set to 0 the 2 registers + TAMP_BACKUP_BRANCH_ADDRESS + TAMP_BACKUP_MAGIC_NUMBER when magic is not egual to BOOT_API_A7_CORE0_MAGIC_NUMBER This patch solve issue for cpu1 restart in kernel. echo 0 > /sys/devices/system/cpu/cpu1/online echo 1 > /sys/devices/system/cpu/cpu1/online Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: cosmetic: bsec: reorder include filesPatrick Delaunay2019-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Reorder the include files in alphabetic order. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: migrate PREBOOT to KconfigPatrick Delaunay2019-05-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use Kconfig to activate CONFIG_PREBOOT (empty by default). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: Move ENV_SIZE and ENV_OFFSET to KconfigPatrick Delaunay2019-05-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add arch stm32mp for ENV migration step and drop more items from include/configs/xxx.h. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: Move config SYS_MALLOC_LEN to KconfigPatrick Delaunay2019-05-231-0/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the the config SYS_MALLOC_LEN to Kconfig as it is already done for zynq arch in commit 01aa5b8f0503 ("Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2019-05-242-3/+46
|\ \ \ | | | | | | | | | | | | - Enable DM for SATA, SDHC, USB in T2080QDS
| * | | powerpc: mpc85xx: delete FSL_SATA for T2080QDS board.Peng Ma2019-05-231-3/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arch: powerpc: add sata node for t2080 dtsPeng Ma2019-05-231-0/+16
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arch: powerpc: add usb node in t2080 dtsYinbo Zhu2019-05-231-0/+19
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
| * | | arch: powerpc: add eSDHC node to t2080qds dtsYinbo Zhu2019-05-231-0/+10
| |/ / | | | | | | | | | | | | Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* | | m68k: add dspi chip-select supportAngelo Dureghello2019-05-246-3/+139
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Angelo Dureghello <angelo@sysam.it> Changes for v5: - new patch
* | | m68k: move dspi bus control functions into cf_spi.c driverAngelo Dureghello2019-05-242-166/+41
| | | | | | | | | | | | | | | | | | | | | This patches move dspi bus-related operations into more proper location, to avoid the driver to declares them as externs. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
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