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* fdt: Move fdt_fixup_ethernet to a common placeTom Rini2017-05-0110-66/+0
| | | | | | | | | | | | | | | | | | | | | | | | With 3f66149d9fb4 we no longer have a common call fdt_fixup_ethernet. This was fine to do on PowerPC as they largely had calls already in ft_cpu_fixup. On ARM however we largely relied on this call. Rather than introduce a large number of changes to ft_cpu_fixup / ft_board_fixup we recognize that this is a common enough call that we should be doing it in a central location. Do it early enough that we can do any further updates in ft_cpu_fixup / ft_board_fixup. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Thomas Chou <thomas@wytron.com.tw> (maintainer:NIOS) Cc: York Sun <york.sun@nxp.com> (maintainer:POWERPC MPC85XX) Cc: Stefan Roese <sr@denx.de> (maintainer:POWERPC PPC4XX) Cc: Simon Glass <sjg@chromium.org> Cc: Joakim Tjernlund <Joakim.Tjernlund@infinera.com> Fixes: 3f66149d9fb4 ("Remove extra fdt_fixup_ethernet() call") Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_CMD_DIAG to KconfigSimon Glass2017-04-302-0/+2
| | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_DIAG Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply CMD_DIAG on some keymile configs] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_CMD_DEKBLOB to KconfigSimon Glass2017-04-301-0/+9
| | | | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_DEKBLOB Note: This option does not seem to actually be enabled by any board. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply under SECURE_BOOT for mx5/6/7] Signed-off-by: Tom Rini <trini@konsulko.com>
* fs: Kconfig: Add a separate option for FS_CRAMFSSimon Glass2017-04-304-0/+6
| | | | | | | | | | | Rather than using CMD_CRAMFS for both the filesystem and its command, we should have a separate option for each. This allows us to enable CRAMFS support without the command, if desired, which reduces U-Boot's size slightly. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply FS_CRAMFS for keymile] Signed-off-by: Tom Rini <trini@konsulko.com>
* fs: Convert CONFIG_CMD_CRAMFS to KconfigSimon Glass2017-04-304-0/+6
| | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_CRAMFS Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply CMD_CRAMFS for keymile] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_CMD_CLK to KconfigSimon Glass2017-04-301-0/+1
| | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_CLK Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply CMD_CLK on ARCH_ZYNQ] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_CMD_CHIP_CONFIG to KconfigSimon Glass2017-04-301-0/+8
| | | | | | | This converts the following to Kconfig: CONFIG_CMD_CHIP_CONFIG Signed-off-by: Simon Glass <sjg@chromium.org>
* fs: Kconfig: Add a separate config for FS_CBFSSimon Glass2017-04-301-0/+1
| | | | | | | | | | | Rather than using CMD_CBFS for both the filesystem and its command, we should have a separate option for each. This allows us to enable CBFS support without the command, if desired, which reduces U-Boot's size slightly. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply FS_CBFS on SYS_COREBOOT] Signed-off-by: Tom Rini <trini@konsulko.com>
* fs: Convert CONFIG_CMD_CBFS to KconfigSimon Glass2017-04-301-0/+1
| | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_CBFS Signed-off-by: Simon Glass <sjg@chromium.org> [trini: imply CMD_CBFS on SYS_COREBOOT] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_CMD_BMODE to KconfigSimon Glass2017-04-301-0/+14
| | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_BMODE Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Make this default y and depend on mx5/6/7] Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_CMD_BLOB to KconfigSimon Glass2017-04-302-2/+0
| | | | | | | | | This converts the following to Kconfig: CONFIG_CMD_BLOB Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add imply CMD_BLOB under CHAIN_OF_TRUST] Signed-off-by: Tom Rini <trini@konsulko.com>
* power: Rename CONFIG_AS3722_POWER to CONFIG_PMIC_AS3722Simon Glass2017-04-301-1/+1
| | | | | | Before converting this to Kconfig, rename it to match the other PMICs. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Re-sync ARCH_MX5 / MX51 / MX53 CONFIG optionsTom Rini2017-04-302-50/+43
| | | | | | | A few boards had not been fully re-synced with CONFIG_ARCH_MX5 / CONFIG_MX51 / CONFIG_MX53 being in Kconfig. Do so now. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'xilinx-fixes-for-v2017.05' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-04-271-0/+1
|\ | | | | | | | | | | | | Xilinx fixes for v2017.05 - Fix usbotg on Miami board - Cleanup zc1751 defconfig
| * zynq-topic-miami.dts: Add usbotg0 alias to make USB actually workMike Looijmans2017-04-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following problem: zynq-uboot> run dfu_ram Setting bus to 1 g_dnl_register: failed!, error: -19 The cause appears to be that the USB framework is looking for a usbotg aliases, so add the alias to point to our USB device. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm/lib/bootm.c: keep ARM v7M in thumb mode during boot_jump_linux()Patrice Chotard2017-04-271-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM v7M, the processor will return to ARM mode when executing a blx instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb mode. Tested on STM32f746-disco board Similar commit: f99993c10882f7dc8ec35993d5febe59aac01e6a Author: Matt Porter <mporter@konsulko.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: omap2+: rename config to ARCH_OMAP2PLUS and consolidate KconfigMasahiro Yamada2017-04-276-177/+173
| | | | | | | | | | | | | | | | | | | | | | | | In Linux, CONFIG_ARCH_OMAP2PLUS is used for OMAP2 or later SoCs. Rename CONFIG_ARCH_OMAP2 to CONFIG_ARCH_OMAP2PLUS to follow this naming. Move the OMAP2+ board/SoC choice down to mach-omap2/Kconfig to slim down the arch/arm/Kconfig level. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Kconfig: Enable FIT support by default for TI platformsAndrew F. Davis2017-04-271-0/+2
| | | | | | | | | | | | | | | | Almost all TI defconfigs enable this already, add this as a default and remove the explicit assignment. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: Warn that starting with v2018.01 gcc-6 or later is requiredTom Rini2017-04-271-1/+11
| | | | | | | | | | | | | | | | | | | | There are more and more cases where if we do not use gcc-6.0 or later we run into problems where our binaries are too large for the targets. Given the prevalence of gcc-6.0 or later toolchains at this point in time, we give notice now that starting with v2018.01 we will require gcc-6 (or later) for ARM. Signed-off-by: Tom Rini <trini@konsulko.com>
* | dm: sandbox: pwm: Add a basic pwm testSimon Glass2017-04-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | Unfortunately a test for the PWM uclass was not included when it was submitted. This was noticed when trying to add more functionality: http://patchwork.ozlabs.org/patch/748172/ Add a simple test to get us started. Signed-off-by: Simon Glass <sjg@chromium.org>
* | OMAP3: Correct name of omap34xx_gpios when using DM_GPIOAdam Ford2017-04-271-1/+1
| | | | | | | | | | | | | | | | The name of the gpio bank under DM_GPIO appear to be a copy-paste error. This changes the name of the gpio bank from am33xx_gpios to omap34xx_gpios. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | omap3: i2c: correct registerAdam Ford2017-04-271-1/+13
|/ | | | | | | | | The register names and offset were not correct as per the TRM for OMAP3530 and OMAP3630. Correct the naing and offsets per the documentation Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge git://git.denx.de/u-boot-sunxiTom Rini2017-04-2522-136/+1050
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| * sunxi: add support for Lichee Pi ZeroIcenowy Zheng2017-04-212-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: add DTSI file for V3sIcenowy Zheng2017-04-211-0/+284
| | | | | | | | | | | | | | | | | | | | | | As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: add basic V3s supportIcenowy Zheng2017-04-213-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basic U-Boot support is now present for V3s. Some memory addresses are changed specially for V3s, as the original address map cannot fit into a so small DRAM. As the DRAM controller code needs a big refactor, the SPL support is disabled in this version. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add clock support for DE2/HDMI/TCON on newer SoCsJernej Skrabec2017-04-202-1/+93
| | | | | | | | | | | | | | | | This is needed for HDMI, which will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: video: Convert lcdc to use struct display_timingJernej Skrabec2017-04-201-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Video driver for older Allwinner SoCs uses cfb console framework which in turn uses struct ctfb_res_modes to hold timing informations. However, DM video framework uses different structure - struct display_timing. It makes more sense to convert lcdc to use new timing structure because all new drivers should use DM video framework and older drivers might be rewritten to use new framework too. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: video: Split out TCON codeJernej Skrabec2017-04-202-103/+128
| | | | | | | | | | | | | | | | | | TCON unit has similar layout and functionality also on newer SoCs. This commit splits out TCON code for easier reuse later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add support for Bananapi M2 UltraChen-Yu Tsai2017-04-203-0/+254
| | | | | | | | | | | | | | | | | | | | | | The Bananapi M2 Ultra is the first publicly available development board featuring the R40 SoC. This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, as well as a defconfig for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add PSCI support for R40Chen-Yu Tsai2017-04-201-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R40's CPU controls are a combination of sun6i and sun7i. All controls are in the CPUCFG block, and it seems the R40 does not have a PRCM block. The core reset, power gating and clamp controls are grouped like sun6i. Last, the R40 does not have a secure SRAM block. This patch adds a PSCI implementation for CPU bring-up and hotplug for the R40. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Fix CPUCFG address for R40Chen-Yu Tsai2017-04-201-2/+4
| | | | | | | | | | | | | | | | The R40 has the CPUCFG block at the same address as the A20. Fix it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Use H3/A64 DRAM initialization code for R40Chen-Yu Tsai2017-04-206-18/+133
| | | | | | | | | | | | | | | | | | | | The R40 seems to have a variant of the memory controller found in the H3 and A64 SoCs. Adapt the code for use on the R40. The changes are based on released DRAM code and comparing register dumps from boot0. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Set PLL lock enable bits for R40Chen-Yu Tsai2017-04-202-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has an extra "PLL lock control" register in the CCU, which controls whether the individual PLL lock status bits in each PLL's control register work or not. This patch enables it for all the PLLs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Fix watchdog reset function for R40Chen-Yu Tsai2017-04-203-7/+8
| | | | | | | | | | | | | | | | The watchdog found on the R40 SoC is the older variant found on the A20. Add the proper "#if defines" to make it work. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Enable AXP221s in I2C mode with the R40 SoCChen-Yu Tsai2017-04-201-0/+7
| | | | | | | | | | | | | | | | | | | | The R40 SoC uses the AXP221s in I2C mode to supply power. Some regulator's common usages have changed, and also the recommended voltage for existing usages have changed. Update the defaults to match. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * sunxi: Add initial support for R40Chen-Yu Tsai2017-04-202-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The R40 is the successor to the A20. It is a hybrid of the A20, A33 and the H3. The R40's PIO controller is compatible with the A20, Reuse the A20 UART and I2C muxing code by adding the R40's macro. The display pipeline is the newer DE 2.0 variant. Block enabling video on R40 for now. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-04-257-32/+111
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| * | arm: psci: make psci usable on single core socsYuantian Tang2017-04-245-30/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Add validation of PPA image from NAND and SDSumit Garg2017-04-241-2/+70
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND FlashSumit Garg2017-04-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Kconfig option to support loading PPA header from eMMC/SD and NAND Flash. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2017-04-253-0/+76
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| * | | arm: socfpga: add cyclone5 based de10-nano boardDalon Westergreen2017-04-253-0/+76
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
* | | ARM: dts: uniphier: sync Device Tree with LinuxMasahiro Yamada2017-04-204-55/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Use - instead of @ for OPP tables - Add input-delay properties to Cadence eMMC nodes - Restore full license text because code-diff is annoying - Fix NAND compatible strings Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: show STM (SCP) status on boot and pinmon commandMasahiro Yamada2017-04-203-8/+48
| | | | | | | | | | | | | | | | | | | | | | | | The SCP (System Control Processor) or what we call STM (Stand-by MPU) is integrated in LD4, Pro4, sLD8, LD6b, LD11, and LD20. For these SoCs, show the information if STM is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: enable PSCI sysreset for uniphier_v8_defconfigMasahiro Yamada2017-04-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This configuration is supposed to be used with ARM Trusted Firmware, so the SYSTEM_RESET is implemented in BL31. Invoke PSCI instead of U-Boot's own reset code because we need to coordinate with SCP (System Control Processor) for the system-level power management. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: setup EHCI PHY paramters for LD11Masahiro Yamada2017-04-202-0/+10
|/ / | | | | | | | | | | Set the same PHY parameters as the Boot ROM uses. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-04-1818-54/+118
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| * | powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ramRuchika Gupta2017-04-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/ unlocks both L1 and L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQYangbo Lu2017-04-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Current sysclk fixing would fix all clocks with 'fixed-clock' compatible. This patch is to fix sysclk by path to avoid any incorrect fixing. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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