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* x86: simplify ljmp to 32-bit codeMasahiro Yamada2019-12-081-3/+1
* x86: use data32 directive instead of macro for operand-size prefixMasahiro Yamada2019-12-081-5/+3
* common: Move board_get_usable_ram_top() out of common.hSimon Glass2019-12-0211-0/+11
* common: Move enable/disable_interrupts out of common.hSimon Glass2019-12-021-0/+1
* common: Move interrupt functions into a new headerSimon Glass2019-12-025-0/+5
* common: Move ARM cache operations out of common.hSimon Glass2019-12-021-0/+1
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-024-0/+4
* common: Move checkcpu() out of common.hSimon Glass2019-12-0211-0/+11
* x86: Quieten TPL's jump_to_image_no_args()Simon Glass2019-11-031-1/+1
* x86: Don't print CPU info in TPLSimon Glass2019-11-031-5/+0
* x86: Move CPU init to before spl_init()Simon Glass2019-11-033-0/+10
* x86: Add a CPU init function for TPLSimon Glass2019-11-032-0/+17
* x86: tpl: Add a fake PCI busSimon Glass2019-11-031-0/+25
* x86: spl: Support init of a PUNITSimon Glass2019-11-032-0/+41
* x86: timer: Use a separate flag for whether timer is initedSimon Glass2019-11-031-0/+1
* binman: x86: Separate out 16-bit reset and init codeSimon Glass2019-10-151-0/+9
* x86: Reduce resetvec sizeSimon Glass2019-10-111-3/+0
* x86: Drop RESET_SEG_SIZESimon Glass2019-10-112-6/+0
* x86: Drop RESET_BASESimon Glass2019-10-111-1/+0
* x86: Update Kconfig options for FSP1Simon Glass2019-10-111-7/+7
* x86: Add a function to find the size of an mrccache recordSimon Glass2019-10-111-7/+8
* x86: Panic when SPL or TPL failSimon Glass2019-10-112-2/+2
* x86: Use mtrr_commit() with FSP2Simon Glass2019-10-081-7/+15
* x86: cpu: Don't include the cpu driver in TPLSimon Glass2019-10-081-1/+4
* x86: Add a function to set variable MTRRsSimon Glass2019-10-082-0/+50
* x86: Refactor mtrr_commit() to allow for shared codeSimon Glass2019-10-081-7/+12
* x86: Allow the PCH and LPC uclasses to work with of-platdataSimon Glass2019-10-081-0/+2
* x86: Add new common CPU functions for turbo/burst modeSimon Glass2019-10-082-0/+110
* x86: Tidy up some duplicate MSR definesSimon Glass2019-10-084-74/+54
* x86: Add common functions for TDP and perf controlSimon Glass2019-10-087-33/+52
* x86: Use a common bus clock for Intel CPUsSimon Glass2019-10-087-14/+10
* x86: Add a common function to set CPU thermal targetSimon Glass2019-10-084-41/+37
* x86: Use a common definition of MSR_IA32_PERF_CTLSimon Glass2019-10-084-5/+3
* x86: pci: Drop the first parameter in pci_x86_r/w_config()Simon Glass2019-10-084-28/+17
* x86: Move acpi_s3.h to a common locationSimon Glass2019-10-088-137/+7
* x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMITSimon Glass2019-10-082-3/+2
* x86: Add various MTRR indexes and valuesSimon Glass2019-10-082-0/+23
* x86: Add more comments to the start-up codeSimon Glass2019-10-083-3/+17
* x86: Change condition for using CARSimon Glass2019-10-082-2/+10
* x86: fsp: Save usable RAM and hob_list in the handoff areaSimon Glass2019-10-083-0/+24
* x86: spl: Move broadwell-specific code out of generic x86 splSimon Glass2019-10-083-5/+12
* x86: spl: Reduce priority of the basic SPL image loaderSimon Glass2019-10-083-6/+6
* x86: spl: Use hang() instead of a while() loopSimon Glass2019-10-082-4/+2
* x86: pci: Add a function to clear and set PCI config regsSimon Glass2019-10-082-0/+59
* x86: Add binman symbols to the imageSimon Glass2019-10-081-0/+6
* x86: Move common Intel CPU info code into a functionSimon Glass2019-10-084-14/+32
* x86: fsp: Add access to variable MRC dataSimon Glass2019-10-083-0/+23
* x86: fsp: Add a few more definitions for FSP2Simon Glass2019-10-081-1/+14
* x86: fsp: Move common support functions into a common fileSimon Glass2019-10-083-167/+177
* x86: Move common fsp functions into a common fileSimon Glass2019-10-085-97/+122
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