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* Merge branch 'next'Tom Rini2022-04-043-13/+6
|\ | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * event: Convert arch_cpu_init_dm() to use eventsSimon Glass2022-03-103-13/+6
| | | | | | | | | | | | | | Instead of a special function, send an event after driver model is inited and adjust the boards which use this function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Revert "x86: Move FACP table into separate functions"Andy Shevchenko2022-03-311-0/+15
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before the culprit patch (see BugLink for the details): => acpi list Name Base Size Detail ---- -------- ----- ------ RSDP 000e4500 24 v02 U-BOOT RSDT 000e4530 38 v01 U-BOOT U-BOOTBL 20220401 INTL 0 XSDT 000e45e0 4c v01 U-BOOT U-BOOTBL 20220401 INTL 0 CSRT 000e5490 58 v00 U-BOOT U-BOOTBL 20220401 INTL 0 FACP 000e54f0 114 v06 U-BOOT U-BOOTBL 20220401 INTL 0 DSDT 000e4780 c06 v02 U-BOOT U-BOOTBL 10000 INTL 20200925 FACS 000e4740 40 MCFG 000e5610 3c v01 U-BOOT U-BOOTBL 20220401 INTL 0 SPCR 000e5650 50 v02 U-BOOT U-BOOTBL 20220401 INTL 0 APIC 000e56a0 48 v02 U-BOOT U-BOOTBL 20220401 INTL 0 After the culprit patch: => acpi list Name Base Size Detail ---- -------- ----- ------ RSDP 000e4500 24 v02 U-BOOT RSDT 000e4530 34 v01 U-BOOT U-BOOTBL 20220401 INTL 0 XSDT 000e45e0 44 v01 U-BOOT U-BOOTBL 20220401 INTL 0 CSRT 000e53a0 58 v00 U-BOOT U-BOOTBL 20220401 INTL 0 MCFG 000e5520 3c v01 U-BOOT U-BOOTBL 20220401 INTL 0 SPCR 000e5560 50 v02 U-BOOT U-BOOTBL 20220401 INTL 0 APIC 000e55b0 48 v02 U-BOOT U-BOOTBL 20220401 INTL 0 As a result Linux kernel can't find mandatory tables and fails to boot. Hence, revert it for good. This reverts commit 379d3c1fd6aa490b1ad5697525cfc89b615cf25a. BugLink: https://lore.kernel.org/all/20220131225930.GJ7515@bill-the-cat/ Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* acpi: Move MCFG implementation to common libMoritz Fischer2022-02-091-54/+0
| | | | | | | | | | MCFG tables are used on multiple arches. Move to common ACPI lib. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Use sizeof(*mcfg) instead of sizeof(*header) Signed-off-by: Simon Glass <sjg@chromium.org>
* arch: x86: lib: acpi_table: Fix MCFG entriesMoritz Fischer2022-02-091-0/+2
| | | | | | | | | | | Commit d953137526cc ("x86: Move SSDT table to a writer function") introduced a bug where the actual MCFG entries are no longer generated. Cc: Simon Glass <sjg@chromium.org> Fixes: d953137526cc ("x86: Move SSDT table to a writer function") Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Move acpi_get_rsdp_addr() ACPI tables to the writerSimon Glass2022-01-251-21/+0
| | | | | | | | | | | | | | | Move this over to use a writer file, moving the code from the x86 implementation. There is no need to store a separate variable since we can simply access the ACPI context. With this, the original monolithic x86 function for writing ACPI tables is gone. Note that QEMU has its own implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move device-specific ACPI tables to a writer functionSimon Glass2022-01-251-2/+0
| | | | | | | Move this over to use a writer function, moving the code from the x86 implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move CSRT table to a writer functionSimon Glass2022-01-251-49/+13
| | | | | | | Move this table over to use a writer function, moving the code from the x86 implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move TCPA table to a writer functionSimon Glass2022-01-251-22/+16
| | | | | | Move this table over to use a writer function, for x86 only. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move MADT table to a writer functionSimon Glass2022-01-251-11/+14
| | | | | | Move this table over to use a writer function, for x86 only. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move TPM2 table to a writer functionSimon Glass2022-01-251-21/+18
| | | | | | Move this table over to use a writer function, for x86 only. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move SSDT table to a writer functionSimon Glass2022-01-251-63/+30
| | | | | | | Move this table over to use a writer function, moving the code from the x86 implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move FACP table into separate functionsSimon Glass2022-01-251-15/+0
| | | | | | | | | Each board has its own way of creating this table. Rather than calling the acpi_create_fadt() function for each one from a common acpi_write_fadt() function, just move the writer into the board-specific code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: Move FADT table to a writer functionSimon Glass2022-01-251-7/+15
| | | | | | Move this table over to use a writer function, for x86 only. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move GNVS table to a writer functionSimon Glass2022-01-251-37/+36
| | | | | | | Move this table over to use a writer function, for x86 only. Handle the two cases Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move DSDT table to a writer functionSimon Glass2022-01-251-42/+7
| | | | | | | | | | | | Move this table over to use a writer function, moving the code from the x86 implementation. Add a pointer to the DSDT in struct acpi_ctx so we can reference it later. Disable this table for sandbox since we don't actually compile real ASL code. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move FACS table to a writer functionSimon Glass2022-01-251-24/+2
| | | | | | | | | Move this table over to use a writer function, moving the code from the x86 implementation. Add a pointer to the DSDT in struct acpi_ctx so we can reference it later. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move base tables to a writer functionSimon Glass2022-01-251-2/+0
| | | | | | | Use the new ACPI writer to write the base tables at the start of the area, moving this code from the x86 implementation. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Use the ACPI table writerSimon Glass2022-01-251-17/+4
| | | | | | | | | | Use the new ACPI writer to write the ACPI tables. At present this is all done in one monolithic function. Future work will split this out. Unfortunately the QFW write_acpi_tables() function conflicts with the 'writer' version, so disable that for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Split out context creation from base tablesSimon Glass2022-01-251-3/+3
| | | | | | | | | | | | | | At present acpi_setup_base_tables() both sets up the ACPI context and writes out the base tables. We want to use an ACPI writer to write the base tables, so split this function into two, with acpi_setup_ctx() doing the context set, and acpi_setup_base_tables() just doing the base tables. Disable the writer's write_acpi_tables() function for now, to avoid build errors. It is enabled in a following patch. Signed-off-by: Simon Glass <sjg@chromium.org>
* acpi: Use finer-grained control of ACPI-table generationSimon Glass2022-01-251-1/+1
| | | | | | | | | Rather than keying everything off ACPIGEN, use the main GENERATE_ACPI_TABLE option to determine whether the core ACPI code is included. Make sure these option are not enabled in SPL/TPL since we never generate tables there. Signed-off-by: Simon Glass <sjg@chromium.org>
* doc: replace @return by Return:Heinrich Schuchardt2022-01-192-6/+6
| | | | | | | | | | | | Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* x86: efi: Round out the link script for 64-bit EFISimon Glass2022-01-151-1/+4
| | | | | | | Make sure the linker lists are in the right place and drop the eh_frame section, which is not needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: efi: Tweak the code used for the 64-bit EFI appSimon Glass2022-01-152-3/+4
| | | | | | | | Add an empty CPU init function to avoid fiddling with low-level CPU features in the app. Set up the C runtime correctly for 64-bit use and avoid clearing BSS, since this is done by EFI when U-Boot is loaded. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Don't process the kernel command line unless enabledSimon Glass2021-12-311-5/+8
| | | | | | | | | | | If the 'bootm' command is not enabled then this code is not available and this causes a link error. Fix it. Note that for the EFI app, there is no indication of missing code. It just hangs! Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* x86: Allow booting a kernel from the EFI appSimon Glass2021-12-311-4/+7
| | | | | | | At present this is disabled, but it should work so long as the kernel does not need EFI services. Enable it and add a note about remaining work. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Show some EFI info with the bdinfo commandSimon Glass2021-10-212-0/+23
| | | | | | | | | | | | | | | | It is useful to see some basic EFI info with the command as it forms part of the information about a board. Add a hook for this and show the table address as a start. While here, fix an invalid cast in setup_efi_info(). Note that this function is using a data structure defined by Linux so we cannot change it. Also note that ulong is used since this is the standard in U-Boot (>6k uses), despite there being quite a bit of the more verbose uintptr_t (930 uses). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* x86: Create a new header for EFISimon Glass2021-10-211-0/+1
| | | | | | | | | | | | The setup routines are called from zimage but don't really belong in the zimage header. Add a new EFI header to house these. Add comments so it is clear what the functions do. Note that these functions are x86-specific. The zimage business is not used on other architectures. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* WS cleanup: remove SPACE(s) followed by TABWIP/2021-09-30-whitespace-cleanupsWolfgang Denk2021-09-301-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass2021-09-251-1/+1
| | | | | | | Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
* treewide: Simply conditions with the new OF_REALSimon Glass2021-09-251-1/+1
| | | | | | | Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
* lmb: x86: Add arch_lmb_reserve()Marek Vasut2021-09-231-0/+18
| | | | | | | | | | | Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic(). It is rather likely this architecture also needs to cover U-Boot with LMB before booting Linux. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini <trini@konsulko.com>
* Remove #include <version.h> from files which do not need itPali Rohár2021-09-171-1/+0
| | | | | Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini2021-08-023-20/+40
|\ | | | | | | | | | | | | | | | | | | | | | | | | - Fixed broken ICH SPI driver in software sequencer mode - Added "m25p,fast-read" to SPI flash node for x86 boards - Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds - Define a default TSC timer frequency for all x86 boards - x86 MTRR MSR programming codes bug fixes - x86 "hob" command bug fixes - Don't program MTRR for DRAM for FSP1 - Move INIT_PHASE_END_FIRMWARE to FSP2 - Use external graphics card by default on Intel Crown Bay - tangier: Fix DMA controller IRQ polarity in CSRT
| * x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWAREBin Meng2021-08-032-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | For FSP1, there is no such INIT_PHASE_END_FIRMWARE. Move board_final_cleanup() to fsp2 directory. Fixes: 7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Don't program MTRR for DRAM for FSP1Bin Meng2021-08-031-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several outstanding issues as to why this does not apply to FSP1: * For FSP1, the system memory and reserved memory used by FSP are already programmed in the MTRR by FSP. * The 'mtrr_top' mistakenly includes TSEG memory range that has the same RES_MEM_RESERVED resource type. Its address is programmed and reported by FSP to be near the top of 4 GiB space, which is not what we want for SDRAM. * The call to mtrr_add_request() is not guaranteed to have its size to be exactly the power of 2. This causes reserved bits of the IA32_MTRR_PHYSMASK register to be written which generates #GP. For FSP2, it seems this is necessary as without this, U-Boot boot process on Chromebook Coral goes very slowly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
* | global: Convert simple_strtoul() with hex to hextoul()Simon Glass2021-08-021-7/+7
|/ | | | | | | | | It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* smbios: error handling for invalid addressesHeinrich Schuchardt2021-07-241-2/+11
| | | | | | | | | | | SMBIOS tables only support 32bit addresses. If we don't have memory here handle the error gracefully: * on x86_64 fail to start U-Boot * during UEFI booting ignore the missing table Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Ensure the e820 map is installed in all casesSimon Glass2021-07-151-4/+4
| | | | | | | | | | This is a revert of a recent logic change in setup_zimage(). We do actually need to install this information always. Change it to install from the Coreboot tables if available, else the normal source. Fixes: e7bae8283fe ("x86: Allow installing an e820 when booting from coreboot") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Do cache set-up by default when booting from corebootSimon Glass2021-07-151-4/+14
| | | | | | | | | | | | | A recent change to disable cache setup when booting from coreboot assumed that this has been done by SPL. The result is that for the coreboot board, the cache is disabled (in start.S) and never re-enabled. If the cache was turned off, as it is on boards without SPL, we should turn it back on. Add this new condition. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop _X86EMU_env definition when CONFIG_BIOSEMU is usedBin Meng2021-07-071-0/+2
| | | | | | | | | | | | | | | | | With x86 we can execute an option ROM either natively or using the x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share the _X86EMU_env variable, with the native code using it to hold register state during interrupt processing. At present, in 32-bit U-Boot, the variable is declared twice, once in common code and once in code only compiled with CONFIG_BIOSEMU. With GCC 11 this causes a 'multiple definitions' error on boards with CONFIG_BIOSEMU. Drop the emulator definition when CONFIG_BIOSEMU is used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-242-5/+6
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2021-03-271-1/+1
| | | | | | | | | The _SUPPORT suffix is from an earlier time and interferes with use of the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix. Tidy up the TODO that prompted this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Don't setup MTRR when booting from corebootSimon Glass2021-03-271-3/+3
| | | | | | | This currently hangs and it is not necessary in any case. Drop the code when booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Don't notify if booted from corebootSimon Glass2021-03-271-0/+4
| | | | | | | | | | When booting from coreboot there is no need to notify the FSP of anything, since coreboot has already done it. Nor it is possible, since the FSP details are not provided by coreboot. Skip it in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Don't enable FSP graphics if booted from corebootSimon Glass2021-03-271-1/+1
| | | | | | | | This driver cannot work when booted from coreboot, since the FSP information is not available. Disable it in that case, so that the coreboot video driver can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Allow installing an e820 when booting from corebootSimon Glass2021-03-273-2/+53
| | | | | | | | Move this code into a generic location so that it can be used by other x86 boards which want to boot from coreboot. Also ensure that this is called if booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Update parsing of the latest sysinfoSimon Glass2021-03-271-22/+235
| | | | | | | | | | Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move coreboot sysinfo parsing into generic x86 codeSimon Glass2021-03-273-0/+262
| | | | | | | | It is useful to be able to parse coreboot tables on any x86 build which is booted from coreboot. Add a new Kconfig option to enable this feature and move the code so it can be used on any board, if enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Sync up timestamp codesSimon Glass2021-03-271-1/+1
| | | | | | | | | | | Add new timestamp codes that are present in coreboot, so that we can decode these in U-Boot. At present TS_U_BOOT_START_KERNEL is used twice. It should only be used just before jumping to Linux, so update the other call site to use TS_START_KERNEL. Signed-off-by: Simon Glass <sjg@chromium.org>
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