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* Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini2021-08-023-20/+40
|\ | | | | | | | | | | | | | | | | | | | | | | | | - Fixed broken ICH SPI driver in software sequencer mode - Added "m25p,fast-read" to SPI flash node for x86 boards - Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds - Define a default TSC timer frequency for all x86 boards - x86 MTRR MSR programming codes bug fixes - x86 "hob" command bug fixes - Don't program MTRR for DRAM for FSP1 - Move INIT_PHASE_END_FIRMWARE to FSP2 - Use external graphics card by default on Intel Crown Bay - tangier: Fix DMA controller IRQ polarity in CSRT
| * x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWAREBin Meng2021-08-032-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | For FSP1, there is no such INIT_PHASE_END_FIRMWARE. Move board_final_cleanup() to fsp2 directory. Fixes: 7c73cea44290 ("x86: Notify the FSP of the 'end firmware' event") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Don't program MTRR for DRAM for FSP1Bin Meng2021-08-031-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several outstanding issues as to why this does not apply to FSP1: * For FSP1, the system memory and reserved memory used by FSP are already programmed in the MTRR by FSP. * The 'mtrr_top' mistakenly includes TSEG memory range that has the same RES_MEM_RESERVED resource type. Its address is programmed and reported by FSP to be near the top of 4 GiB space, which is not what we want for SDRAM. * The call to mtrr_add_request() is not guaranteed to have its size to be exactly the power of 2. This causes reserved bits of the IA32_MTRR_PHYSMASK register to be written which generates #GP. For FSP2, it seems this is necessary as without this, U-Boot boot process on Chromebook Coral goes very slowly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax Tested-by: Simon Glass <sjg@chromium.org>
* | global: Convert simple_strtoul() with hex to hextoul()Simon Glass2021-08-021-7/+7
|/ | | | | | | | | It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* smbios: error handling for invalid addressesHeinrich Schuchardt2021-07-241-2/+11
| | | | | | | | | | | SMBIOS tables only support 32bit addresses. If we don't have memory here handle the error gracefully: * on x86_64 fail to start U-Boot * during UEFI booting ignore the missing table Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Ensure the e820 map is installed in all casesSimon Glass2021-07-151-4/+4
| | | | | | | | | | This is a revert of a recent logic change in setup_zimage(). We do actually need to install this information always. Change it to install from the Coreboot tables if available, else the normal source. Fixes: e7bae8283fe ("x86: Allow installing an e820 when booting from coreboot") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Do cache set-up by default when booting from corebootSimon Glass2021-07-151-4/+14
| | | | | | | | | | | | | A recent change to disable cache setup when booting from coreboot assumed that this has been done by SPL. The result is that for the coreboot board, the cache is disabled (in start.S) and never re-enabled. If the cache was turned off, as it is on boards without SPL, we should turn it back on. Add this new condition. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop _X86EMU_env definition when CONFIG_BIOSEMU is usedBin Meng2021-07-071-0/+2
| | | | | | | | | | | | | | | | | With x86 we can execute an option ROM either natively or using the x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share the _X86EMU_env variable, with the native code using it to hold register state during interrupt processing. At present, in 32-bit U-Boot, the variable is declared twice, once in common code and once in code only compiled with CONFIG_BIOSEMU. With GCC 11 this causes a 'multiple definitions' error on boards with CONFIG_BIOSEMU. Drop the emulator definition when CONFIG_BIOSEMU is used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek Behún2021-05-242-5/+6
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* cpu: Rename SPL_CPU_SUPPORT to SPL_CPUSimon Glass2021-03-271-1/+1
| | | | | | | | | The _SUPPORT suffix is from an earlier time and interferes with use of the CONFIG_IS_ENABLED() macro. Rename the option to drop the suffix. Tidy up the TODO that prompted this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Don't setup MTRR when booting from corebootSimon Glass2021-03-271-3/+3
| | | | | | | This currently hangs and it is not necessary in any case. Drop the code when booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Don't notify if booted from corebootSimon Glass2021-03-271-0/+4
| | | | | | | | | | When booting from coreboot there is no need to notify the FSP of anything, since coreboot has already done it. Nor it is possible, since the FSP details are not provided by coreboot. Skip it in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Don't enable FSP graphics if booted from corebootSimon Glass2021-03-271-1/+1
| | | | | | | | This driver cannot work when booted from coreboot, since the FSP information is not available. Disable it in that case, so that the coreboot video driver can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Allow installing an e820 when booting from corebootSimon Glass2021-03-273-2/+53
| | | | | | | | Move this code into a generic location so that it can be used by other x86 boards which want to boot from coreboot. Also ensure that this is called if booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Update parsing of the latest sysinfoSimon Glass2021-03-271-22/+235
| | | | | | | | | | Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move coreboot sysinfo parsing into generic x86 codeSimon Glass2021-03-273-0/+262
| | | | | | | | It is useful to be able to parse coreboot tables on any x86 build which is booted from coreboot. Add a new Kconfig option to enable this feature and move the code so it can be used on any board, if enabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Sync up timestamp codesSimon Glass2021-03-271-1/+1
| | | | | | | | | | | Add new timestamp codes that are present in coreboot, so that we can decode these in U-Boot. At present TS_U_BOOT_START_KERNEL is used twice. It should only be used just before jumping to Linux, so update the other call site to use TS_START_KERNEL. Signed-off-by: Simon Glass <sjg@chromium.org>
* cbfs: Allow access to CBFS without a headerSimon Glass2021-03-271-1/+2
| | | | | | | | | | In some cases CBFS does not start with a header but is just a collection of files. It is possible to support this so long as the size of the CBFS is provided. Update the cbfs_init_mem() function to support this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Support a fake PCI device with of-platdata-instSimon Glass2021-03-261-0/+1
| | | | | | | | | | | | | | | | With TPL we don't need full PCI support and it adds to code size. Instead, a simple_bus driver is good enough to be able to read and write the PCI config and do a little basic setup. So at present there are two drivers in U-Boot called pci_x86. One is in UCLASS_PCI, used in SPL and U-Boot proper. The other is in UCLASS_SIMPLE_BUS and used only in TPL. Add a tag to tell dtoc about this, so it knows which one to use when generating the devices and uclasses. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/global_data.h from common headerWIP/2021-02-02-drop-asm_global_data-when-unusedSimon Glass2021-02-0227-0/+27
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: tpl: Show next stage being bootedSimon Glass2021-02-011-1/+6
| | | | | | | | Enhance the debugging to show the next stage being booted as well as a dump of the start of the image. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: spl: Clear BSS unconditionallySimon Glass2021-02-011-1/+1
| | | | | | | | This should be done even if not using TPL, since BSS may be in use or boards that only use SPL. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: zimage: Improve command-line debug handlingSimon Glass2021-02-011-3/+7
| | | | | | | | | | At present if the command line is very long it is truncated by the printf() statement, which works within a limited buffer. Use puts() instead. Also show better debugging with the command-line setup fails. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: zimage: Allow dumping the image from outside the moduleSimon Glass2021-02-011-8/+15
| | | | | | | | | | | At present it is possible to dump an image within the zimage command, but it is also useful to be able to dump it from elsewhere, for example in a loader that has special handling for the different zimage stages. Export this feature as a new function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini2021-01-051-1/+3
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * x86: tpl: Remove unwanted devicetree stringSimon Glass2021-01-051-1/+3
| | | | | | | | | | | | | | | | Update this driver to use of_match_ptr(). This reduces the TPL binary size by about 32 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-051-7/+8
|\ \ | |/ |/| | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * x86: zimage: Update cmdline parameter to be an env varSimon Glass2020-12-161-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the updated changes to bootargs substitution[1], the zboot command needs to be updated to get its command line from an environment variable instead of a memory address. This is because the command-line string must be updated to convert %U to ${uuid}, etc. In any case it is more flexible to use a environment variable and it is best to do this before the release to avoid a subsequent change. Update the command accordingly. [1] http://patchwork.ozlabs.org/project/uboot/list/?series=212481 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-134-5/+5
| | | | | | | | | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-134-5/+5
| | | | | | | | | | | | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: zimage: Add silent-console processingSimon Glass2020-12-041-0/+14
|/ | | | | | | | | | At present zimage does its own command-line processing and does not support the 'silent console' feature. There doesn't seem to be any good reason for this. Add support for silent console to zimage. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: zimage: Quieten down the zimage boot processSimon Glass2020-11-061-5/+6
| | | | | | | | | Much of the output is not very useful. The bootm command is quite a bit quieter. Convert some output to use log_debug(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
* x86: zimage: Sanity-check the kernel version before printing itSimon Glass2020-11-061-0/+9
| | | | | | | | | | | With Chrome OS the kernel setup block is stored in a separate place from the kernel, so it is not possible to access the kernel version string. At present, garbage is printed. Add a sanity check to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: zimage: Add a little more loggingSimon Glass2020-11-061-0/+6
| | | | | | | | Add logging for each part of the boot process, using a new Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
* x86: fsp: Adjust calculations for MTRR range and DRAM topSimon Glass2020-11-061-13/+22
| | | | | | | | | | | | | | | | | | | | At present the top of available DRAM is the same as the top of the range of the low-memory MTRR. In fact, U-Boot is allowed to use memory up until the start of the FSP reserved memory. Use that value for low_end, since it makes more memory available. Keep the same calculation as before for mtrr_top, i.e. the top of reserved memory. A side-effect of this change is that the E820 tables have a single entry that extends from the bottom of the memory used by U-Boot to the bottom of the FSP reserved memory. This includes the bloblist, if ACPI tables are placed there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Don't show the UART address by defaultSimon Glass2020-11-061-1/+1
| | | | | | | | | | | | This is useful when using Linux's earlycon since the MMIO address must be provided on some platforms, e.g.: earlycon=uart8250,mmio32,0xddffc000,115200n8 However this is only for debugging, so don't show it by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Include the TPMv1 table only if neededSimon Glass2020-11-061-8/+11
| | | | | | | | This table is not needed if a v2 TPM is in use. Add a condition to avoid adding it when not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Silence some logging statementsSimon Glass2020-11-062-2/+2
| | | | | | | | Quite a few log_info() calls are included in the x86 code which should use log_debug() instead. Convert them to reduce unwanted output. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Convert fsp_dram to use log_debug()Simon Glass2020-11-061-2/+6
| | | | | | | | Use log_debug() instead of debug() in this file, to enable the extra features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass2020-11-061-1/+1
| | | | | | | | | | | | | | | At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* acpi: Don't reset the tables with every new generationSimon Glass2020-11-061-0/+1
| | | | | | | | | At present if SSDT and DSDT code is created, only the latter is retained for examination by the 'acpi items' command. Fix this by only resetting the list when explicitly requested. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Put the generated code first in DSDTSimon Glass2020-11-061-9/+18
| | | | | | | | | | | The current implementation for DSDT tables is not correct for the case where there is generated code, as the length ends up being incorrect. Also, we want the generated code to go first in the table. Rewrite this piece to correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Allow the SSDT to be emptySimon Glass2020-11-061-7/+15
| | | | | | | | If there is nothing in the SSDT we should not include it in the tables. Update the implementation to check this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Show the interrupt pointer with 'irqinfo'Simon Glass2020-11-061-0/+3
| | | | | | | | It is useful for this command to show the address of the interrupt table. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: nhlt: Fix a few bugs in the table generationSimon Glass2020-11-061-1/+3
| | | | | | | | At present these tables do not have the correct header, and there is an occasional incorrect value due to uninited data. Fix these bugs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: nhlt: Correct output of bytes and 16-bit dataSimon Glass2020-11-061-3/+10
| | | | | | | | At present these functions are incorrect. Fix them and add some logging and checking to avoid future problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow putting some tables in the bloblistSimon Glass2020-11-061-3/+46
| | | | | | | | | | | | | | | | | | | | | | At present all tables are placed starting at address f0000 in memory, and can be up to 64KB in size. If the tables are very large, this may not provide enough space. Also if the tables point to other tables (such as console log or a ramoops area) then we must allocate other memory anyway. The bloblist is a nice place to put these tables since it is contiguous, which makes it easy to reserve this memory for linux using the 820 tables. Add an option to put some of the tables in the bloblist. For SMBIOS and ACPI, create suitable pointers from the f0000 region to the new location of the tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/project/uboot/patch/ 20201105062407.1.I8091ad931cbbb5e3b6f6ababdf3f8d5db0d17bb9@changeid/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use if instead of #ifdef in write_tables()Simon Glass2020-11-051-19/+19
| | | | | | | Use if() to remove the extra build path in this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: acpi: Store the ACPI context in global_dataSimon Glass2020-11-051-1/+6
| | | | | | | | | | | At present we create the ACPI context but then drop it after generation of tables is complete. This is annoying because we have to then search for tables later. To fix this, allocate the context and store it in global_data. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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