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* x86: mtrr: Fix function descriptionsWolfgang Wallner2021-04-151-2/+2
| | | | | | | | Fix copy/paste errors in the descriptions of mtrr_close () and mtrr_set(). Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Allow init of debug UART in U-Boot properSimon Glass2021-03-271-0/+1
| | | | | | | | | | | At present the debug UART is only set up in SPL, on the assumption that the boot flow will always pass through there. When booting from coreboot, SPL is not used, so the debug UART is not available. Move the code into a common place so that it can be used in U-Boot proper also. Add the required init to start_from_spl.S as well. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Allow installing an e820 when booting from corebootSimon Glass2021-03-271-1/+15
| | | | | | | | Move this code into a generic location so that it can be used by other x86 boards which want to boot from coreboot. Also ensure that this is called if booting from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Update parsing of the latest sysinfoSimon Glass2021-03-272-35/+290
| | | | | | | | | | Quite a few new tag types have been added over the years. Bring these into U-Boot so that all required tags can be parsed. Add a proper comment to struct sysinfo_t while we are here, since many of the meanings are not obvious. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Sync up timestamp codesSimon Glass2021-03-271-1/+63
| | | | | | | | | | | Add new timestamp codes that are present in coreboot, so that we can decode these in U-Boot. At present TS_U_BOOT_START_KERNEL is used twice. It should only be used just before jumping to Linux, so update the other call site to use TS_START_KERNEL. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Move coreboot timestamp info into coreboot_tables.hSimon Glass2021-03-272-24/+39
| | | | | | | | This all relates to the sysinfo structure provided by coreboot. Put the timestamp definitions into the same file as the others. Tidy up a few comments at the same time. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Make coreboot sysinfo available to any x86 boardSimon Glass2021-03-271-0/+0
| | | | | | | | | It is possible to boot U-Boot for chromebook_coral either 'bare metal' or from coreboot. In the latter case we want to provide access to the coreboot sysinfo tables. Move the definitions into a file available to any x86 board. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'v2021.04-rc4' into nextTom Rini2021-03-151-0/+4
|\ | | | | | | Prepare v2021.04-rc4
| * x86: Fix member check in intel_gnvsSimon Glass2021-03-091-0/+4
| | | | | | | | | | | | | | | | When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | gpio: x86: Drop the deprecated methods in intel_gpioSimon Glass2021-03-031-0/+5
|/ | | | | | | We don't need to implement direction_input() and direction_output() anymore. Drop them and use update_flags() instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/global_data.h from common headerWIP/2021-02-02-drop-asm_global_data-when-unusedSimon Glass2021-02-027-2/+14
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* x86: zimage: Allow dumping the image from outside the moduleSimon Glass2021-02-011-0/+10
| | | | | | | | | | | At present it is possible to dump an image within the zimage command, but it is also useful to be able to dump it from elsewhere, for example in a loader that has special handling for the different zimage stages. Export this feature as a new function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update Chromium OS GNVS namesSimon Glass2021-02-011-6/+28
| | | | | | | | | | | The Global Non-Volatile Storage struct has some fields with particular meanings. Rename these to make things easier to follow. Also add a few more boot flags. GNVS should not be confused with GNVQ (Going Nowhere Very Quickly). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Support TPM and RTC in SPLSimon Glass2021-01-301-0/+3
| | | | | | | | Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Adjust how the UART gets its platform dataSimon Glass2021-01-051-1/+18
| | | | | | | | | | | | At present this driver calls malloc() to start a new platform data structure, fills it in and tells driver model to use it. We want to avoid malloc, particularly with the new version of of-platdata. Create a new struct which encompasses both the dtd struct and the ns16550 one, to avoid this. Unfortunately we must copy the data into the right place for the ns16550 driver. Add some comments about this. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: sysreset: Move priv/plat structs to headersSimon Glass2021-01-051-0/+18
| | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them and add the dtd struct too. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: Move priv/plat structs for intel_common to headersSimon Glass2021-01-052-0/+39
| | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Move priv/plat structs to headersSimon Glass2021-01-053-0/+62
| | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Fix header guard in asm/pmu.hSimon Glass2021-01-051-3/+3
| | | | | | This has the wrong name. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
* fsp: Move and rename fsp_types.h fileSughosh Ganu2020-12-312-63/+2
| | | | | | | | | | | | The fsp_types.h header file contains macros for building signatures of different widths. These signature macros are architecture agnostic, and can be used in all places which use signatures in a data structure. Move and rename the fsp_types.h under the common include header. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop unnecessary mp_init logicSimon Glass2020-12-181-1/+1
| | | | | | | | | | Now that sequence numbers are set up when devices are bound, this code is not needed. Also, we should use dev_seq() instead of req_seq. Update the whole file accordingly. Also fix up APL cpu while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-132-2/+2
| | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-131-4/+3
| | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-131-1/+1
| | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass2020-11-061-3/+0
| | | | | | | | | | | | | | | At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Define the Chrome OS GNVS regionSimon Glass2020-11-061-1/+50
| | | | | | | | | It is not possible to boot Chrome OS properly without passing some basic information from U-Boot. This applies even if verified boot is not being used. Add a structure definition for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Show the interrupt pointer with 'irqinfo'Simon Glass2020-11-061-0/+17
| | | | | | | | It is useful for this command to show the address of the interrupt table. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow writing tables to failSimon Glass2020-11-051-1/+3
| | | | | | | | At present write_tables() can fail but does not report this problem to its caller. Fix this by changing the return type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a layout for Chrome OS verified bootSimon Glass2020-11-051-0/+38
| | | | | | | Add definitions for part of the vboot context used with verified boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Add core init for the SoCSimon Glass2020-11-053-1/+42
| | | | | | | | Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for more than 8 MTRRsSimon Glass2020-09-251-3/+12
| | | | | | | | | At present the mtrr command only support 8 MTRRs. Some SoCs have more than that. Update the implementation to support up to 10. Read the number of MTRRs dynamically instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: hob: Try to show a name instead of a GUIDSimon Glass2020-09-251-0/+25
| | | | | | | | | | | | | GUIDs are one of the seven evils of the computer world. They obfuscate the meaning and require people to look up long hex strings to decode it. Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use. Add a way to decode the GUIDs known to U-Boot. Add a few more to the list for good measure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a header guard to asm/acpi_table.hSimon Glass2020-09-251-0/+4
| | | | | | | | This file cannot currently be included in ASL files. Add a header guard to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Correct the assembly guard in e820.hSimon Glass2020-09-251-2/+1
| | | | | | | | This is currently in the wrong place, so including the file in the device tree fails. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: cpu: Report address width from cpu_get_info()Simon Glass2020-09-251-0/+9
| | | | | | | Add support for this new field in the common code used by most x86 CPU drivers. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Update the FSP API with the end-firmware methodSimon Glass2020-09-251-3/+12
| | | | | | | | | | | This new method is intended to be called when UEFI shuts down the 'boot services', i.e. any lingering code in the boot loader that might be used by the OS. Add a definition for this new method and update the comments a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Generate required ACPI tablesSimon Glass2020-09-251-0/+18
| | | | | | | Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Allow reading hostbridge base addressesSimon Glass2020-09-251-0/+31
| | | | | | | Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Add support for additional Intel tablesSimon Glass2020-09-251-0/+115
| | | | | | | Apollo Lake needs to generate a few more table types used on Intel SoCs. Add support for these into the x86 ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Add common Intel ACPI tablesSimon Glass2020-09-253-0/+81
| | | | | | | Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Add PCT and PTC tablesSimon Glass2020-09-251-0/+35
| | | | | | | These are needed for the CPU tables. Add them into an x86-specific file since we do not support them on sandbox, or include tests. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Support generation of the DBG2 tableSimon Glass2020-09-251-0/+11
| | | | | | | | | | | | Add an implementation of the DBG2 (Debug Port Table 2) ACPI table. Adjust one of the header includes to be in the correct order, before adding more. Note that the DBG2 table is generic but the PCI UART is x86-specific at present since it assumes an ns16550 UART. It can be generalised later if necessary. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Support generation of the HPET tableSimon Glass2020-09-251-0/+10
| | | | | | | Add an implementation of the HPET (High Precision Event Timer) ACPI table. Since this is x86-specific, put it in an x86-specific file Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a few common Intel CPU functionsSimon Glass2020-09-251-0/+49
| | | | | | Add functions to query CPU information, needed for ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Update iomap for ACPISimon Glass2020-09-251-0/+16
| | | | | | | Add some more definitions to the iomap. These will be used by ACPI-generation code as well as the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Add power-management definitionsSimon Glass2020-09-251-1/+39
| | | | | | | | | Add SCI and power-state definitions required by ACPI tables. Fix the license to match the original source file. Als update the guard on acpi_pmc.h to avoid an error when buiding ASL. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add some definitions for SMMSimon Glass2020-09-251-0/+27
| | | | | | | U-Boot does not support SMM (System Management Mode) at present, but needs a few definitions to correctly set up the ACPI table. Add these. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: apl: Support writing the IntelGraphicsMem tableSimon Glass2020-09-251-0/+247
| | | | | | | This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add wake sources for the acpi_gpe driverSimon Glass2020-09-252-0/+138
| | | | | | | | | | Some devices can wake the system from sleep, e.g opening the lid on a clamshell or moving a USB mouse. Add a wake to specify this for USB devices and add the settings for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: acpi: Expand the GNVSSimon Glass2020-09-252-1/+2
| | | | | | | Expand this to 4KB so that it is possible to add custom information to it. On Chromebooks this is used to pass verified-boot information. Signed-off-by: Simon Glass <sjg@chromium.org>
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