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* x86: coral: Show memory config and SKU ID on startupSimon Glass2021-03-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide the model information through sysinfo so that it shows up on boot. For memconfig 4 pins are provided, for 16 combinations. For SKU ID there are two options: - two pins provided in a ternary arrangement, for 9 combinations. - reading from the EC Add a binding doc and drop the unused #defines as well. Example: U-Boot 2021.01-rc5 CPU: Intel(R) Celeron(R) CPU N3450 @ 1.10GHz DRAM: 3.9 GiB MMC: sdmmc@1b,0: 1, emmc@1c,0: 2 Video: 1024x768x32 @ b0000000 Model: Google Coral (memconfig 5, SKU 3) This depends on the GPIO series: http://patchwork.ozlabs.org/project/uboot/list/?series=228126 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Fall back to coreboot video when FSP missingSimon Glass2021-03-271-0/+5
| | | | | | | | When booting from coreboot the FSP video information is no-longer available. Enable the coreboot driver so that we can get some sort of display in this case. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coral: Update the SD card-detect GPIOSimon Glass2021-03-271-1/+1
| | | | | | | | | Since the recent bug fix, it doesn't matter which GPIO phandle is used so long as the GPIO number is right. Still, we may as well use the correct one to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* x86: coral: Put the eMMC firstSimon Glass2021-03-271-0/+1
| | | | | | | | | | | At present the eMMC device does not have an alias so it appears after the SD card which is device 1. There is no device 0 which is odd. Make the eMMC device be the first one. Update the boot script to use the new device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* x86: dts: Drop unused CONFIG_SPLSimon Glass2021-03-261-5/+1
| | | | | | | This cannot be used since the previous #elif has already dealt with SPL. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Make use of binman expanded entriesSimon Glass2021-03-261-10/+1
| | | | | | | | We don't need to spell out the separate pieces of U-Boot phase binaries anymore. Revert to using the simple entry and let binman do the expansion itself as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coral: Drop TPM and ACPI interrupts from TPLSimon Glass2021-03-261-5/+5
| | | | | | | | | | | These devices are not actually built in TPL but are currently active in the TPL devicetree. For of-platdata-inst this means that we will try to generate devices for them, which fails. Update them to be active only in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Don't include reset driver in SPLSimon Glass2021-03-261-1/+1
| | | | | | | | We don't normally need this driver in TPL/SPL, so drop it for now. It can be enabled by individual boards if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coral: Add a devicetree node for eMMCSimon Glass2021-02-011-0/+6
| | | | | | | | | Add a node for this so we can indicate that it is does not require any ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Support TPM and RTC in SPLSimon Glass2021-01-301-1/+19
| | | | | | | | Update the devicetree so that the TPM and RTC can be used in SPL. Also enable the pins used for getting the memory configuration settings while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coral: Update an unused pin to reduce powerSimon Glass2021-01-301-0/+1
| | | | | | GPIO_25 is not used on coral, so set it up in deep sleep. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini2021-01-052-7/+17
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * x86: Drop rtc from SPLSimon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | The RTC is not currently used in SPL. Drop it so that it does not take up space. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: coral: Remove unwanted nodes from SPL/TPLSimon Glass2021-01-051-6/+11
| | | | | | | | | | | | | | | | Some devices are not needed in SPL/TPL. For TPL this causes the generation of unnecessary of-platadata structs. Make some adjustments to fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: coral: Move fsp-m settings to a subnodeSimon Glass2021-01-051-0/+5
| | | | | | | | | | | | | | | | | | At present these settings are in the node for host-bridge and so are visible in TPL as well as SPL. But they are only used for SPL. Move them to a subnode so that TPL does not included them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: edison: Switch to DM_USB_GADGETAndy Shevchenko2020-12-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | DM is the modern default approach for the drivers in U-Boot. It also allows to configure code via Device Tree. Move Intel Edison to use DM_USB_GADGET and drop hard coded values. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: edison: Use dwc3-generic driver for Intel EdisonAndy Shevchenko2020-12-161-0/+4
| | | | | | | | | | | | | | | | | | Use generic Synopsys DesignWare 3 driver on Intel Edison. For now it's just a stub which allows future refactoring. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: edison: Add CPU to compatible stringAndy Shevchenko2020-12-161-1/+1
|/ | | | | | | | Like in the rest of x86 boards append CPU to the board compatible string. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Update smbios tables to latest definitionSimon Glass2020-11-101-6/+21
| | | | | | | | The accepted binding uses multiple nodes, one for each table type. Update coral accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Provide default SMBIOS manufacturer/productSimon Glass2020-11-0615-0/+60
| | | | | | | | | | | | | | Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to be passed through the C preprocessor. Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: reword the commit message a little bit] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: galileo: Use devicetree for SMBIOS settingsSimon Glass2020-11-061-0/+28
| | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use CONFIG_CHROMEOS_VBOOT for verified bootSimon Glass2020-11-062-2/+2
| | | | | | | | | | | | | | | At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add SMBIOS info for CoralSimon Glass2020-11-051-0/+8
| | | | | | | | This is required by Chrome OS so that the audio and other unibuild features work correctly. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Drop the duplicate PCIe settingsSimon Glass2020-11-051-2/+0
| | | | | | | | | These settings are included twice. The second lot are correct, so drop the others. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for private filesSimon Glass2020-11-051-0/+4
| | | | | | | | | | | Some boards need to include binary data into the image for use during the boot process. Add a node for these. An example is the audio-codec configuration used by some audio drivers on Intel platforms. If no private files are provided, they will be omitted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: edison: Generate an image suitable for xFSTKSimon Glass2020-09-251-0/+34
| | | | | | | | | | | | | It is useful to be able to flash Edison directly without relying on the installed U-Boot being functional. Add a binman image for this. It includes a 'OSIP' header (which happens to look like an MBR / (Master-Boot Record), U-Boot binary and an environment. I am not able to find a specification for OSIP. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: Use multiple imagesSimon Glass2020-09-253-21/+10
| | | | | | | | | | We already use binman's 'multiple-images' feature with Chrome OS and we want to use it for Edison. There is no real down-side. Adjust x86 to always use multiple-images. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* x86: coral: Update config and device tree for ACPISimon Glass2020-09-251-14/+212
| | | | | | | Enable new features and provide require device-tree config so that U-Boot produces the correct ACPI tables on Coral. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: chromebook_panther: Correct the image layoutSimon Glass2020-07-281-1/+5
| | | | | | | | This board does not have microcode but at present that is not supported by Kconfig nor the binman image layout. Fix both of these. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move the fdtmap away from the binary blobsSimon Glass2020-07-281-2/+2
| | | | | | | | This causes conflicts on chromebook_link64. Move it to after U-Boot where there should be plenty of space. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Support a warning message when DRAM init is slowSimon Glass2020-07-171-0/+1
| | | | | | | | | | | | | | | | With DDR4, Intel SOCs take quite a long time to init their memory. During this time, if the user is watching, it looks like SPL has hung. Add a message in this case. This works by adding a return code to fspm_update_config() that indicates whether MRC data was found and a new property to the device tree. Also add one more debug message while starting. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
* x86: coral: Correct some FSP-S settingsSimon Glass2020-06-021-7/+3
| | | | | | | | | | | | | | Some settings were modified slightly in the device-tree conversion. Return these to their original values. This includes some audio settings and a few others that have changed. Note that we still rely on the FSP defaults for most values, so there is no need to specify a value if the FSP default is suitable. This makes WiFi work again. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Correct some FSP-M settingsSimon Glass2020-06-021-0/+5
| | | | | | | | Some settings were modified slightly in the device-tree conversion. Return these to their original values. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Use devicetree for FSP-S configurationBernhard Messerklinger2020-05-271-7/+28
| | | | | | | | | | | | | | | A the moment the FSP-S configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-S full configurable from devicetree by adding binding properties for all FSP-S parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Use devicetree for FSP-M configurationBernhard Messerklinger2020-05-271-1/+37
| | | | | | | | | | | | | | | | | | A the moment the FSP-M configuration is a mix of hard coded values and devicetree properties. This patch makes FSP-M full configurable from devicetree by adding binding properties for all FSP-M parameters. Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral) [sjg: Fix a build error for coral] Signed-off-by: Simon Glass <sjg@chromium.org> [bmeng: Add __maybe_unused to fsp_update_config_from_dtb()] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow building an SPL image for corebootSimon Glass2020-05-041-0/+18
| | | | | | | | | | Coreboot runs in 32-bit mode and cannot run a 64-bit U-Boot. To get around this we can build a combined image with 32-bit SPL and 64-bit U-Boot. Add a build rule and binman definition for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* tpm: cr50: Use the correct GPIO bindingSimon Glass2020-04-161-1/+1
| | | | | | | This device should use ready-gpios rather than ready-gpio. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: p2sb: Drop 'apl' prefixWolfgang Wallner2020-03-051-1/+1
| | | | | | | | | | | | | Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coral: Add I2C and TPM device-tree definitionsSimon Glass2020-02-071-0/+88
| | | | | | | | Add nodes to the device tree for Cr50 and other available I2C ports. Also enable the ACPI interrupt driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: apl: Use the clock driverSimon Glass2020-02-071-0/+5
| | | | | | | Enable the Intel clock driver and modify coral's device tree to use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: itss: Remove apl-prefixWolfgang Wallner2020-02-041-1/+1
| | | | | | | | | The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so remove the apl-prefix of the implemented functions/structures/... Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move coreboot over to use the coreboot UARTSimon Glass2020-02-041-1/+5
| | | | | | | | Use this UART to improve the compatibility of U-Boot when used as a coreboot payload. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add chromebook_coralSimon Glass2019-12-152-0/+832
| | | | | | | | | Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Separate out U-Boot and device tree in ROM imageSimon Glass2019-12-151-3/+11
| | | | | | | | | | | | | | | | | | At present binman does not support updating a device tree that is part of U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get updated entry information. This makes binman_entry_find() work correctly. Do the same for SPL tool. In both cases, group the two parts into a section so that SPL symbols get the correct total size. It may be possible for binman to handle this automatically at some point, by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and u-boot.dtb Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Don't repeat microcode in U-Boot if not neededSimon Glass2019-12-151-0/+7
| | | | | | | | | At present if SPL sets up the microcode then it is still included in U-Boot as well. This is wasteful as microcode is large. Adjust the logic in the image to prevent this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an fdtmap and image-headerSimon Glass2019-12-151-0/+5
| | | | | | | | | Add these entries to the ROM so that we can list the contents of an image with 'binman ls'. The image-header is not essential but does speed up access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an option to control the position of SPLSimon Glass2019-12-151-2/+2
| | | | | | | | | | | For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different location from where SPL must be placed in ROM. In other words, although SPL runs before SDRAM is set up, it is not execute-in-place (XIP). Add a Kconfig option for the ROM position. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an option to control the position of U-BootSimon Glass2019-12-151-15/+3
| | | | | | | | | | | | The existing work-around for positioning U-Boot in the ROM when it actually runs from RAM still exists and there is not obvious way to change this. Add a proper Kconfig option to handle this case. This also adds a new bool property to indicate whether CONFIG_SYS_TEXT_BASE exists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update .dtsi file for FSP2Simon Glass2019-12-151-1/+31
| | | | | | | | | | Include the IFWI section and the FSP-M binary. The FSP-T binary is not currently used, as CAR is set up manually. Also drop the FSP binary as this relates only to FSP1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Disable microcode section for FSP2Simon Glass2019-12-151-0/+7
| | | | | | | | | At present we don't support loading microcode with FSP2. The correct way to do this is by adding it to the FIT. For now, disable including microcode in the image. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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