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* riscv: add option to wait for ack from secondary harts in smp functionsLukas Auer2019-12-105-12/+28
* riscv: add functions for reading the IPI statusLukas Auer2019-12-104-0/+43
* riscv: dts: Add #address-cells and #size-cells in nor nodeRick Chen2019-12-102-2/+6
* riscv: dts: Support four cores SMPRick Chen2019-12-102-6/+108
* riscv: Fix clear bss loop in the start-up codeRick Chen2019-12-103-4/+4
* riscv: ax25: cache: Add SPL_RISCV_MMODE for SPLRick Chen2019-12-101-14/+46
* riscv: andes_plic: Fix some wrong configurationsRick Chen2019-12-101-4/+7
* riscv: ax25: add SPL supportRick Chen2019-12-101-1/+3
* riscv: dts: Add hifive-unleashed-a00 dts from LinuxJagan Teki2019-12-103-0/+348
* riscv: increase stack size to avoid a stack overflow during distro bootLukas Auer2019-12-101-1/+1
* common: Move board_get_usable_ram_top() out of common.hSimon Glass2019-12-021-0/+1
* common: Move enable/disable_interrupts out of common.hSimon Glass2019-12-021-0/+1
* common: Move interrupt functions into a new headerSimon Glass2019-12-021-0/+1
* common: Move ARM cache operations out of common.hSimon Glass2019-12-023-0/+3
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-023-0/+3
* RISC-V: Align boot image header with LinuxAtish Patra2019-10-181-5/+6
* gpio: sifive: add support for DM based gpio driver for FU540-SoCSagar Shrikant Kadam2019-10-182-0/+41
* riscv: cache: use CCTL to flush d-cacheRick Chen2019-09-031-9/+13
* riscv: dts: move out AE350 L2 node from cpus nodeRick Chen2019-09-032-12/+22
* riscv: cache: Flush L2 cache before jump to linuxRick Chen2019-09-031-0/+17
* riscv: ax25: add imply v5l2 cache controllerRick Chen2019-09-031-0/+1
* riscv: andes_plic: init plic by scanning each cpu nodeRick Chen2019-09-031-11/+25
* riscv: update fix_rela_dynMarcus Comstedt2019-09-031-5/+5
* riscv: add a generic FIT generator scriptLukas Auer2019-08-261-0/+100
* riscv: support SPL stack and global data relocationLukas Auer2019-08-261-1/+34
* riscv: add SPL supportLukas Auer2019-08-267-1/+190
* riscv: add run mode configuration for SPLLukas Auer2019-08-267-18/+44
* riscv: Access CSRs using CSR numbersBin Meng2019-08-154-243/+19
* riscv: Sync csr.h with Linux kernel v5.2Bin Meng2019-08-152-16/+114
* env: Drop environment.h header file where not neededSimon Glass2019-08-111-1/+0
* efi_loader: use predefined constants in crt0_*_efi.SHeinrich Schuchardt2019-07-161-6/+5
* riscv: Add Microchip MPFS Icicle board supportPadmarao Begari2019-06-051-0/+4
* CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner2019-05-182-4/+18
* CONFIG_SYS_[DI]CACHE_OFF: convert to KconfigTrevor Woerner2019-05-181-0/+12
* RISCV: image: Add booti supportAtish Patra2019-05-092-0/+56
* riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen2019-05-092-0/+4
* riscv: Introduce CONFIG_XIP to support booting from flashRick Chen2019-05-096-0/+21
* dts: switch spi-flash to jedec, spi-nor compatibleNeil Armstrong2019-04-122-2/+2
* riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failureRick Chen2019-04-081-0/+2
* riscv: dts: ae350 support SMPRick Chen2019-04-082-44/+118
* riscv: ax25: Andes specific cache shall only support in M-modeRick Chen2019-04-081-0/+1
* riscv: ax25: Add platform-specific Kconfig optionsRick Chen2019-04-081-0/+6
* riscv: Add a SYSCON driver for Andestech's PLMTRick Chen2019-04-085-0/+67
* riscv: Add a SYSCON driver for Andestech's PLICRick Chen2019-04-085-2/+127
* riscv: hang if relocation of secondary harts failsLukas Auer2019-04-081-1/+12
* riscv: do not rely on hart ID passed by previous boot stageLukas Auer2019-04-081-0/+4
* riscv: boot images passed to bootm on all hartsLukas Auer2019-04-081-1/+12
* riscv: add support for multi-hart systemsLukas Auer2019-04-085-2/+147
* riscv: save hart ID in register tp instead of s0Lukas Auer2019-04-081-2/+2
* riscv: delay initialization of caches and debug UARTLukas Auer2019-04-081-8/+8
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