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* riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is ena...Rick Chen2019-05-092-0/+4
* riscv: Introduce CONFIG_XIP to support booting from flashRick Chen2019-05-092-0/+8
* riscv: ax25: Andes specific cache shall only support in M-modeRick Chen2019-04-081-0/+1
* riscv: ax25: Add platform-specific Kconfig optionsRick Chen2019-04-081-0/+6
* riscv: hang if relocation of secondary harts failsLukas Auer2019-04-081-1/+12
* riscv: do not rely on hart ID passed by previous boot stageLukas Auer2019-04-081-0/+4
* riscv: add support for multi-hart systemsLukas Auer2019-04-082-2/+141
* riscv: save hart ID in register tp instead of s0Lukas Auer2019-04-081-2/+2
* riscv: delay initialization of caches and debug UARTLukas Auer2019-04-081-8/+8
* riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systemsAnup Patel2019-02-271-0/+20
* riscv: Rename cpu/qemu to cpu/genericAnup Patel2019-02-274-1/+1
* riscv: move the AX25-specific implementation of flush_dcache_allLukas Auer2019-01-151-0/+22
* riscv: Save boot hart id to the global dataBin Meng2018-12-181-0/+4
* riscv: Return to previous privilege level after trap handlingBin Meng2018-12-181-8/+0
* riscv: Fix context restore before returning from trap handlerBin Meng2018-12-181-1/+1
* riscv: Move trap handler codes to mtrap.SBin Meng2018-12-183-90/+112
* riscv: Do some basic architecture level cpu initializationBin Meng2018-12-181-1/+26
* riscv: Update supports_extension() to use desc from cpu driverBin Meng2018-12-181-0/+26
* riscv: Remove non-DM version of print_cpuinfo()Bin Meng2018-12-181-37/+0
* riscv: Probe cpus during bootBin Meng2018-12-182-0/+27
* riscv: qemu: Add platform-specific Kconfig optionsBin Meng2018-12-181-0/+11
* riscv: ax25: Hide the ax25-specific Kconfig optionBin Meng2018-12-182-11/+18
* riscv: qemu: Create a simple-bus driver for the soc nodeBin Meng2018-12-181-0/+14
* riscv: ax25-ae350: Pass dtb address to u-boot with a1 registerRick Chen2018-12-051-2/+0
* riscv: Add kconfig option to run U-Boot in S-modeAnup Patel2018-12-051-8/+15
* riscv: cache: Implement i/dcache [status, enable, disable]Rick Chen2018-11-266-1/+114
* riscv: save hart ID and device tree passed by prior boot stageLukas Auer2018-11-262-2/+16
* riscv: do not blindly modify the mstatus CSRLukas Auer2018-11-261-4/+4
* riscv: remove unused labels in start.SLukas Auer2018-11-261-9/+0
* Drop CONFIG_INIT_CRITICALBin Meng2018-11-261-13/+0
* riscv: align mtvec on a 4-byte boundaryLukas Auer2018-11-261-1/+1
* riscv: fix inconsistent use of spaces and tabs in start.SLukas Auer2018-11-261-161/+161
* riscv: Move do_reset() to a common placeBin Meng2018-10-032-17/+0
* riscv: Add QEMU virt board supportBin Meng2018-10-033-0/+52
* riscv: Make start.S available for all targetsBin Meng2018-10-034-3/+3
* riscv: Add a helper routine to print CPU informationBin Meng2018-10-032-0/+54
* riscv: Fix coding style issues in the linker scriptBin Meng2018-10-031-30/+28
* riscv: Move the linker script to the CPU root directoryBin Meng2018-10-031-0/+0
* riscv: Include bss subsections in linker scriptAlexander Graf2018-08-201-1/+1
* efi_loader: Rename sections to allow for implicit dataAlexander Graf2018-07-251-10/+16
* riscv: cpu: nx25: Rename as ax25Rick Chen2018-05-294-2/+2
* efi_loader: Enable RISC-V supportRick Chen2018-05-291-0/+16
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-074-9/+4
* riscv: ae250: Support DT provided by the board at runtimeRick Chen2018-03-301-0/+2
* riscv: cpu: Add nx25 to support RISC-VRick Chen2018-01-124-0/+403
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