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* mips: octeon: Add bootoctlinux commandAaron Williams2020-10-073-0/+716
| | | | | | | | | | | | Octeon needs a platform specific cmd to boot the Linux kernel, as specific parameters need to be passed and special handling for the multiple cores (SMP) is needed. Co-developed-by: Stefan Roese <sr@denx.de> Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> [use gd->ram_base instead of gd->bd->bi_memstart] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: octeon: Add bootmem supportAaron Williams2020-10-073-0/+1994
| | | | | | | | This is needed for Linux booting, as the memory infos need to be passed in this bootmem format to the Linux kernel. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add coremask supportAaron Williams2020-10-073-0/+1119
| | | | | | | This patch adds the coremask handling functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-bootinfo.hAaron Williams2020-10-071-0/+350
| | | | | | | | Add header to handle bootinfo support, needed for Octeon Linux kernel booting. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-fuse.hAaron Williams2020-10-071-0/+71
| | | | | | | Add header to handle Octeon fuse access. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header octeon-feature.hAaron Williams2020-10-071-0/+442
| | | | | | | | This header includes the Octeon feature detection used in many Octeon drivers. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add header cvmx-regs.hAaron Williams2020-10-071-0/+144
| | | | | | | This header includes common register defines and accessor functions. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: lowlevel_init.S: Add NMI handling code for SMP Linux bootingStefan Roese2020-10-071-0/+76
| | | | | | | | | | | | | This patch adds the necessary lowlevel init code, to enable SMP Linux booting. This code will be used with the platform specific Octeon Linux boot command "bootoctlinux", which starts a configurable number of cores into Linux. Additionally some erratas and lowlevel register initializations are copied from the original Cavium / Marvell U-Boot source code, enabling booting into the Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: octeon-model.h: Enable inclusion from assembler filesStefan Roese2020-10-071-0/+4
| | | | | | | Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header from assembler files. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add USB DT nodesStefan Roese2020-10-072-0/+84
| | | | | | | Add the USB device tree nodes to the Octeon dts/dtsi files. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* mips: octeon: cache.c: Flush all pending writes in flush_dcache_range()Stefan Roese2020-10-071-6/+6
| | | | | | | | As noticed while working on the USB xHCI support, Octeon needs to flush all pending writes so that the values are present in the memory. Add this "syncw" instruction (twice) to flush_dcache_range(). Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add mangle-port.hStefan Roese2020-10-071-0/+56
| | | | | | | | | Import platform specific mangle-port.h header, allowing a area specific swapping, which is needed on Octeon for USB & PCI areas. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: cpu.c: Add table for selective swappingStefan Roese2020-10-071-0/+21
| | | | | | | | | | Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: dram.c: Add RAM driver supportStefan Roese2020-10-071-8/+64
| | | | | | | | | This patch adds the initialization call for the Octeon RAM driver to the Octeon platforms code. So if enabled via Kconfig, the DDR driver will be called and the RAM will be configured and used. If the RAM driver is not enabled, the L2 cache is still used as RAM. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add octeon_ddr.h headerAaron Williams2020-10-071-0/+982
| | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon Add cvmx/cvmx-lmcx-defs.h headerAaron Williams2020-10-071-0/+4574
| | | | | | | | This header will be used by the DDR driver (lmc). Its ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add octeon-model.h headerAaron Williams2020-10-071-0/+313
| | | | | | | | This header is used by the upcoming DDR driver and potentially by other drivers ported from the 2013 Cavium / Marvell U-Boot repository. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT nodeStefan Roese2020-10-071-0/+17
| | | | | | | | This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi file. It also adds the L2C DT node, as this is referenced by the DDR driver. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'next'Tom Rini2020-10-052-2/+2
|\ | | | | | | | | | | | | Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
| * global: Move from bi_memstart/memsize -> gd->ram_base/ram_sizeStefan Roese2020-08-262-2/+2
| | | | | | | | | | | | | | | | | | With the planned removal of bi_memstart & bi_memsize, this patch now moves the references to the better suiting gd->ram_base/ram_size variables. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | mips: vocore2: fix various issuesMauro Condarelli2020-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | - fix SPL image generation - fix incorrect console output - increase malloc_f and malloc_r space to fix LZMA decompression errors - increase SPI flash clock Signed-off-by: Mauro Condarelli <mc5686@mclink.it> [squashed to one patch, fix commit subject and description] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson2020-09-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIO bank name for banks J and K are not correct when using the 'gpio' command from the console. The driver derives the bank name from the device tree instance string by using the instance value and adding 'A': gpio0@xxaddrxx is Bank A, gpio1@yyaddryy is Bank B and so on. On the PIC32, there is no Bank I so instances 8 and 9 need to be incremented as a minimum change. An alternative (less opaque) implementation would be to use a bank-name property instead but this would require modifying the driver code too. Signed-off-by: John Robertson <john.robertson@simiatec.com>
* | mips: dts: Fix PIC32MZDA GPIO register definitionsJohn Robertson2020-09-231-23/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or using the 'gpio' command from the console. The root cause is a discrepancy between the driver and the device tree: the driver code expects an absolute I/O address in the <reg> property, while the device tree defines the address relative to a declaration in the parent pinctrl node. Changing the device tree to fix a driver issue would normally be wrong, however: - I have run the first version of U-Boot in which this driver appears (v2016.03) and the same problem exists, so this is not a regression; - There is no code that references a parent device tree node that might suggest the intent of the author was to parse the DT as it exists now; - The equivalent Linux PIC32 GPIO driver also uses absolute addresses for the GPIO <reg> property. This change brings the U-Boot DT more into line with Linux. Additionally, the data sheet (Microchip ref. 60001361H) shows that the register set to control a GPIO bank spans 0xE0 bytes, but the device tree specified size is only 0x48 bytes. Signed-off-by: John Robertson <john.robertson@simiatec.com>
* | mips: dts: Fix device tree warnings for PIC32MZDAJohn Robertson2020-09-231-0/+11
| | | | | | | | Signed-off-by: John Robertson <john.robertson@simiatec.com>
* | mips: pic32mzdask: disable SDHCI SDCD signal workaroundJohn Robertson2020-09-231-0/+1
|/ | | | | | | | The PIC32MZ DA Starter Kit does not need the card detect workaround because the SDCD signal line is connected properly. Disable the workaround in this case. Signed-off-by: John Robertson <john.robertson@simiatec.com>
* Merge tag 'mips-pull-2020-08-03' of ↵Tom Rini2020-08-043-3/+90
|\ | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - doc: fix qemu-mips build instructions - MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
| * mips: octeon: Update Octeon KconfigStefan Roese2020-08-031-2/+4
| | | | | | | | | | | | | | | | | | This patch selects DM_SPI & DM_I2C for MIPS Octeon. DM_GPIO, DM_SERIAL and DM_ETH are already selected. Additionally the selections are now alphabetically sorted. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: mrvl, octeon-ebb7304.dts: Add SPI flash DT nodeStefan Roese2020-08-031-0/+9
| | | | | | | | | | | | Add the SPI flash DT node for the EBB7304. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: mrvl,cn73xx.dtsi: Add SPI DT nodeStefan Roese2020-08-031-0/+10
| | | | | | | | | | | | Add the Octeon SPI DT node to the dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: dts: Add Octeon clock driver DT nodesStefan Roese2020-08-032-1/+11
| | | | | | | | | | | | | | This patch adds the DT nodes for the Octeon clock support via the common clk_ API. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: dts: Add I2C DT nodesStefan Roese2020-08-032-0/+30
| | | | | | | | | | | | Add I2C DT nodes to the Octeon dts / dtsi files. Signed-off-by: Stefan Roese <sr@denx.de>
| * mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodesStefan Roese2020-08-031-0/+26
| | | | | | | | | | | | Add the Octeon GPIO DT node to the dtsi file. Signed-off-by: Stefan Roese <sr@denx.de>
* | mscc: Drop dm.h header fileSimon Glass2020-08-035-15/+0
|/ | | | | | | This header file should not be included in other header files. Remove it from each one and use a forward declaration instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* mips: octeon: Add minimal Octeon 3 EBB7304 EVK supportStefan Roese2020-07-183-0/+111
| | | | | | | | | | | | | | | This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board. Supported devices: - UART - reset - CFI parallel NOR flash Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: use mips_mach_early_init() to copy to L2 cacheStefan Roese2020-07-182-0/+51
| | | | | | | | | | | | | This patch adds the code to copy itself from bootrom location to a different location (TEXT_BASE) to the Octeon platform. Its used in this case to copy the complete U-Boot image into L2 cache, which greatly improves the bootup time - especially in regard to the very long and complex DDR4 init code. The Kconfig symbol CONFIG_MIPS_MACH_EARLY_INIT is enabled with this patch for Octeon. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: dts: Add Octeon 3 cn73xx base dtsi fileStefan Roese2020-07-181-0/+64
| | | | | | This patch adds the base dtsi file for the Octeon 3 cn73xx SoC. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: octeon: Initial minimal support for the Marvell Octeon SoCAaron Williams2020-07-1812-0/+312
| | | | | | | | | | | | | | This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init codeStefan Roese2020-07-182-0/+14
| | | | | | | | | | | | | | This patch adds the optional call to mips_mach_early_init() to start.S at a very early stage. Its disabled per default. It can be used for very early machine / platform specific init code. Its called very early and at this stage the PC is allowed to differ from the linking address (CONFIG_TEXT_BASE) as no absolute jump has been performed until this call. It will be used by thje Octeon platform. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: sync asm/mipsregs.h with Linux 5.7Daniel Schwierzeck2020-07-185-196/+1103
| | | | | | | | | | Sync asm/mipsregs.h with Linux 5.7. Also replace the custom symbols EBASE_CPUNUM and EBASE_WG with the according symbols from Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: sync asm/addrspace.h with Linux 5.7Daniel Schwierzeck2020-07-181-12/+2
| | | | | | | | Sync asm/addrspace.h with Linux 5.7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: sync asm/asm.h with Linux 5.7Daniel Schwierzeck2020-07-181-120/+10
| | | | | | | | Sync asm/asm.h with Linux 5.7. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: remove deprecated UNCACHED_SDRAM() macroDaniel Schwierzeck2020-07-182-15/+2
| | | | | | | | | | | | This macro only served as a wrapper for CKSEG1ADDR() with an exception for CONFIG_TB0229. CONFIG_TB0229 doesn't exist, thus use CKSEG1ADDR() directly. This also prepares for an upcoming asm header sync with Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: add config options for generic cache setup codeDaniel Schwierzeck2020-07-182-1/+29
| | | | | | | | | | | | | | | | | | Add an own Kconfig symbol for the initial disabling of caches invoked from generic start code. Also add an own Kconfig symbols for the initialization of caches invoked from generic start code. Until now both code paths could only be disabled with CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for RAM boot scenarios like EJTAG or SPL payload or for machines which don't require cache initialization or which want to provide their own cache implementation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: refactor disabling of cachesDaniel Schwierzeck2020-07-182-5/+10
| | | | | | | | | | | Logically this code belongs to cache_init.S. If a complex SoC needs to replace the generic cache init, mips_cache_disable() can now be called from custom start.S files. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: add KSEG1 wrapper for change_k0_ccaDaniel Schwierzeck2020-07-181-14/+18
| | | | | | | | | | | change_k0_cca() is called multiple times. Move the code for changing to KSEG1 to a macro to avoid code duplication. Also fix missing change to KSEG1 when changing to CONF_CM_CACHABLE_COW. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: start.S: remove dead codeDaniel Schwierzeck2020-07-181-9/+0
| | | | | | | | | | Since commit 703ec9ddf965 ("MIPS: Stop building position independent code") the relocation code was completely reworked and removed from start.S. Remove some left-overs of the old code. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: cache: Make invalidate_dcache_range() weak to enable overwriteStefan Roese2020-07-181-1/+1
| | | | | | | | This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This makes it possible to overwrite this function by a platforms specific version, which will be done for Octeon. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: cache: Make flush_cache() weak to enable overwriteStefan Roese2020-07-181-1/+1
| | | | | | | | This patch adds __weak to flush_cache() in lib/cache.c. This makes it possible to overwrite this function by a platforms specific version, like done with the Octeon base port. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CMStefan Roese2020-07-182-2/+12
| | | | | | | | This patch enables the usage of CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM, which is what is needed for the newly added Octeon platform. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usageStefan Roese2020-07-182-4/+5
| | | | | | | | | | | | | | | | | | | | This patch changes the R_MIPS_NONE define from 0 to a magic value. This makes it possible to better detect any forbidden pre-relocation usage of BSS variables, as they are often zero'ed and then relocation is stopped too early. Additionally the error message is improved to also print the faulting address. This helps finding the root-cause for this breakage by comparing this address with the values in System.map. This patch helps a lot when working on pre-relocation code, like the Octeon DDR init code, where such variables have hit me multiple times now. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
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