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* dts: imx53: Add gpio and i2c nodes to imx53.dtsi fileLukasz Majewski2018-05-171-1/+100
| | | | | | Those DTS nodes has been ported from Linux kernel (v4.16) Signed-off-by: Lukasz Majewski <lukma@denx.de>
* mx6: Select CONFIG_MP with MX6_SMPPeter Robinson2018-05-171-0/+1
| | | | | | | It makes sense to select the MP multi processor option at the same time we select the other SMP options needed for SMP capable i.MX6 SoCs. Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
* mx31: Convert MX31_HCLK_FREQ and MX31_CLK32 to Kconfig.Magnus Lilja2018-05-172-8/+14
| | | | | | | | Also remove the #ifdef's from clock.h since the Kconfig values defaults the to old default values in clock.h. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mx31pdk: Convert CONFIG_MX31 flag to use Kconfig.Magnus Lilja2018-05-172-8/+26
| | | | | | | | Move CONFIG_MX31 from mx31pdk.h to mx31pdk_defconfig and introduce necessary Kconfig changes as well. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ge: bx50v3: remove redundant targetsIan Ray2018-05-171-12/+2
| | | | | | | | | This replaces TARGET_GE_B{4,6,8}50V3 with common TARGET_GE_BX50V3. The boards are identified automatically at runtime. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2018-05-153-0/+22
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| * dts: sunxi: add PWM node for sun50iVasily Khoruzhick2018-05-151-0/+9
| | | | | | | | | | | | Add PWM definition to sun50i-a64.dtsi Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
| * pwm: sunxi: add support for PWM found on Allwinner A64Vasily Khoruzhick2018-05-152-0/+13
| | | | | | | | | | | | | | This commit adds basic support for PWM found on Allwinner A64. It can be used for pwm_backlight driver (e.g. for Pinebook) Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
* | net: add Kconfig for MVGBEChris Packham2018-05-141-1/+0
|/ | | | | | | Add Kconfig for MVGBE and update boards to select this. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* ARM: mvebu: a38x: move sys_env_device_rev_getChris Packham2018-05-142-3/+24
| | | | | | | | | | Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESSChris Packham2018-05-141-0/+1
| | | | | | | | | | | PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite only being used in the serdes code. Move this definition to ctrl_pex.h where all the other PEX defines are. Also remove the duplicate definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in ctrl_pex.h. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* arm64: mvebu: Add basic support for the Turris Mox boardMarek Behún2018-05-144-1/+141
| | | | | | | | | | | | | | | | | This adds basic support for the Turris Mox board from CZ.NIC, which is currently being crowdfunded on Indiegogo. Turris Mox is as modular router based on the Armada 3720 SOC (same as EspressoBin). The basic module can be extended by different modules. The device tree binary for the kernel can be dependent on which modules are connected, and in what order. Because of this, the board specific code creates in U-Boot a variable called module_topology, which carries this information. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
* watchdog: Add support for Armada 37xx CPU watchdogMarek Behún2018-05-141-0/+6
| | | | | | | | | | | | | | This adds support for the CPU watchdog found on Marvell Armada 37xx SoCs. There are 4 counters which can be set as CPU watchdog counters. This driver uses the second counter (ID 1, counting from 0) (Marvell's Linux also uses second counter by default). In the future it could be adapted to use other counters, with definition in the device tree. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
* spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequencyMarek Behún2018-05-141-2/+2
| | | | | | | | | | | | Since now we have driver for clocks on Armada 37xx, use it to determine SQF clock frequency for the SPI driver. Also change the default config files for Armada 37xx devices so that the clock driver is enabled by default, otherwise the SPI driver cannot be enabled. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
* driver: clk: Add support for clocks on Armada 37xxMarek Behún2018-05-141-0/+20
| | | | | | | | | | | | | | | | | | | | | | The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* phy: marvell: a3700: Use comphy_mux on Armada 37xx.Marek Behún2018-05-141-2/+3
| | | | | | | | | | | | | | | Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3. This is needed for Armada 37xx. This introduces new device tree bindings. AFAIK there is currently no driver for Armada 37xx comphy in Linux. When such a driver will be pushed into Linux, this will need to be rewritten accordingly. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge git://git.denx.de/u-boot-tegraTom Rini2018-05-112-3/+6
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| * apalis_t30: describe pcie portsMarcel Ziswiler2018-05-101-0/+3
| | | | | | | | | | | | | | Add some more comments describing the various PCIe ports available. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * apalis-tk1: add missing as3722 gpio0 configurationMarcel Ziswiler2018-05-101-3/+3
| | | | | | | | | | | | | | | | | | As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module explicitly configure it to high-impedance as well. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblazeTom Rini2018-05-1114-40/+379
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup
| * | arm: zynqmp: Add ZynqMP minimal R5 supportMichal Simek2018-05-117-0/+153
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot. This patch is adding minimal support to get U-Boot boot. U-Boot on R5 runs out of DDR with default configuration that's why DDR needs to be partitioned if there is something else running on arm64. Console is done via Cadence uart driver and the first Cadence Triple Timer Counter is used for time. This configuration with uart1 was tested on zcu100-revC. U-Boot 2018.05-rc2-00021-gd058a08d907d (Apr 18 2018 - 14:11:27 +0200) Model: Xilinx ZynqMP R5 DRAM: 512 MiB WARNING: Caches not enabled MMC: In: serial@ff010000 Out: serial@ff010000 Err: serial@ff010000 Net: Net Initialization Skipped No ethernet found. ZynqMP r5> There are two ways how to run this on ZynqMP. 1. Run from ZynqMP arm64 tftpb 20000000 u-boot-r5.elf setenv autostart no && bootelf -p 20000000 cpu 4 disable && cpu 4 release 10000000 lockstep or cpu 4 disable && cpu 4 release 10000000 split 2. Load via jtag when directly to R5 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Setup MMU map for DDR at run timeNitin Jain2018-05-112-33/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fills the MMU map for DDR at run time based on information read from Device Tree or automatically detected from static configuration. The patch is needed because for systems which has for example 1GB of memory but MMU map is 2GB there could be spurious accesses which was seen in past when mapping is not fitting with actual memory installed. Signed-off-by: Nitin Jain <nitin.jain@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Enable cadence WDT for zcu100Michal Simek2018-05-112-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable watchdog on zcu100 to make sure if there is a bug in the u-boot there is proper reset. Watchdog expires and PMU fw is informed and based on setting proper action is taken. The patch is enabling reset-on-timeout feature and also fixing fixed clock rate for watchdog where 100MHz is max (and also default) clock value. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm64: zynqmp: Add new defconfig for zc1275 revBSiva Durga Prasad Paladugu2018-05-112-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables support zc1275 revB board. It has SD added compared to revA. The same configuration will work for RevC boards aswell. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: zynq: Remove checkboard and enable DISPLAY_CPUINFOMichal Simek2018-05-111-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that showing silicon version is part of the CPU info display, let's remove checkboard(). Note that the generic show_board_info() will still show the DT 'model' property. For instance: U-Boot 2018.05-rc2-00025-g611b3ee0159b (Apr 19 2018 - 11:23:12 +0200) CPU: Zynq 7z045 Silicon: v1.0 Model: Zynq ZC706 Development Board I2C: ready Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar>, and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> mini configuration doesn't need to show this information. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: zynq: Rework FPGA initializationMichal Simek2018-05-112-1/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit moves the FPGA descriptor definition to mach-zynq, where it makes more sense. Based on patches from Ariel D'Alessandro <ariel@vanguardiasur.com.ar> and Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: zynq: Enable debug_uart_init in spl when enabledMichal Simek2018-05-111-5/+6
| |/ | | | | | | | | | | | | In past this code was commented and was used for debug purpose. But there is no reason not to enabled it based on macros. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-05-116-45/+93
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| * | armv8/fsl-lsch2: make the workaround for PIN MUX erratum A010539 robustHou Zhiqiang2018-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mask HRESET_B after cleared the the RCW_SRC, because in the workaround we override the RCW_SRC and if HRESET_B is issued after the override then SoC cannot find valid RCW as the RCW_SRC was overwritten and result in hang. So we need to mask HRESET_B in case user asserts it, and the PORESET_B should be asserted which leads to resampling of cfg_rcw_src pins and loading of correct RCW_SRC. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/fsl-lsch2: correct QMAN clockHou Zhiqiang2018-05-092-1/+11
| | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: sec_firmware: Add support for multiple loadablesSumit Garg2018-05-091-11/+42
| | | | | | | | | | | | | | | | | | | | | | | | Enable support for multiple loadable images in SEC firmware FIT image. Also add example "sec_firmware_ppa.its" file. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: sec_firmware: Remove JR3 from device tree node in all casesRuchika Gupta2018-05-092-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JR3 was getting removed from device tree only if random number generation was successful. However, if SEC firmware is present, JR3 should be removed from device tree node irrespective of the random seed generation as SEC firmware reserves it for it's use. Not removing it in case of random number generation failure causes the kernel to crash. Random number generation was being called twice. This is not required. If SEC firmware is running, SIP call can be made to the SEC firmware to get the random number. This call itself would return failure if function is not supported. Duplicate calling of random number generation function has been removed. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: layerscape: Avoid code duplication for TZASC InstantiationSriram Dash2018-05-091-28/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | TZASC controller configurations are similar. Put them in a macro and avoid code duplication. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge git://git.denx.de/u-boot-socfpgaTom Rini2018-05-101-2/+2
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| * | | ARM: socfpga: Add boot trampoline for Arria10Marek Vasut2018-05-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arria10 uses slightly different boot image header than the Gen5 SoCs, in particular the header itself contains an offset from the start of the header to which the Arria10 jumps. This offset must not be negative, yet the header is placed at offset 0x40 of the bootable binary. Therefore, to jump into U-Boot, add a trampoline just past the Arria10 boot header and point to this trampoline at fixed offset from the header generated using the mkimage -T socfpgaimage_v1 . Note that it is not needed to jump back to offset 0x0 of the image, it is possible to jump directly at the reset label and save processing two instructions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Chin Liang See <chin.liang.see@intel.com>
* | | | SPDX: Convert a few files that were missed beforeTom Rini2018-05-103-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of the main conversion a few files were missed. These files had additional whitespace after the '*' and before the SPDX tag and my previous regex was too strict. This time I did a grep for all SPDX tags and then filtered out anything that matched the correct styles. Fixes: 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style") Reported-by: Heinrich Schuchardt <xypron.debian@gmx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* | | | bootm: fix 'memory-fixup' for vxWorks bootHannes Schmelzer2018-05-101-1/+1
| |_|/ |/| | | | | | | | | | | | | | | | | The check for having a memory node within the fdt blob is made wrong, we fix this here. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
* | | Merge git://git.denx.de/u-boot-sunxiTom Rini2018-05-097-168/+379
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| * | | board: sunxi: sun8i-v40: Add Bananapi M2 Berry supportJagan Teki2018-05-072-1/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Banana Pi BPI-M2 Berry is a quad-core mini single board computer built with Allwinner V40 SoC. It features - Quad Core ARM Cortex A7 CPU V40 - 1GB of RAM . - microSD/SATA port.. - onboard WiFi and BT - 4 USB A 2.0 ports - 1 USB OTG port - 1 HDMI port - 1 audio jack - DC power port Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * | | ARM: dts: sun8i: Sync r40 dtsi from LinuxJagan Teki2018-05-071-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync sun8i-r40.dtsi changes from Linux with Merge: a406778618d0 088345fc3553 Author: Stephen Rothwell <sfr@canb.auug.org.au> Date: Tue Apr 24 14:15:02 2018 +1000 Merge branch 'akpm/master' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * | | sunxi: Sort dts Makefile entries for H3Chen-Yu Tsai2018-05-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dts Makefile entries for the H3 are not ordered correctly. Move the Nano Pi entries before the Orange Pi so they are. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | sunxi: Add Libre Computer Board ALL-H3-CC H5 ver.Chen-Yu Tsai2018-05-012-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a device tree file for the H5 version of the Libre Computer Board ALL-H3-CC. It is the same board first introduced in commit afe27544125e ("sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H5 SoC, and has 4Gb DDR3 chips instead of 2Gb ones. The device tree utilizes the common board design file for ALL-H3-CC, providing just the model strings and SoC specifics. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | sunxi: Add Libre Computer Board ALL-H3-CC H2+ ver.Chen-Yu Tsai2018-05-012-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a device tree file for the H2+ version of the Libre Computer Board ALL-H3-CC. It is the same board first introduced in commit afe27544125e ("sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H2+ SoC, and has only two 2Gb DDR3 chips instead of four. The device tree utilizes the common board design file for ALL-H3-CC, providing just the model strings and SoC specifics. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | | sunxi: Split out common board design for ALL-H3-CC device treeChen-Yu Tsai2018-05-012-164/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Libre Computer Project ALL-H3-CC has three models, all using the same board design, but with different pin compatible SoCs and amount of DRAM. Currently only the H3 1GB DRAM variant is supported. To support the two other variants, first split the original device tree into a common board design part and an SoC specific part. The SoC part only defines which SoC is used and model name, and includes the SoC specific dtsi file and the common design dtsi file. Also fix up the SPDX identifier line to use the correct comment style, and place it on the first line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | | | arm: bitops: fix find_next_zero_bit() for case size < 32Grygorii Strashko2018-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | find_next_zero_bit() incorrectly handles cases when: - total bitmap size < 32 - rest of bits to process static inline int find_next_zero_bit(void *addr, int size, int offset) { unsigned long *p = ((unsigned long *)addr) + (offset >> 5); unsigned long result = offset & ~31UL; unsigned long tmp; if (offset >= size) return size; size -= result; offset &= 31UL; if (offset) { tmp = *(p++); tmp |= ~0UL >> (32-offset); if (size < 32) [1] goto found_first; if (~tmp) goto found_middle; size -= 32; result += 32; } while (size & ~31UL) { tmp = *(p++); if (~tmp) goto found_middle; result += 32; size -= 32; } [2] if (!size) return result; tmp = *p; found_first: [3] tmp |= ~0UL >> size; ^^^ algo can reach above line from from points: [1] offset > 0 and size < 32, tmp[offset-1..0] bits set to 1 [2] size < 32 - rest of bits to process in both cases bits to search are tmp[size-1..0], but line [3] will simply set all tmp[31-size..0] bits to 1 and ffz(tmp) below will fail. example: bitmap size = 16, offset = 0, bitmap is empty. code will go through the point [2], tmp = 0x0 after line [3] => tmp = 0xFFFF and ffz(tmp) will return 16. found_middle: return result + ffz(tmp); } Fix it by correctly seting tmp[31..size] bits to 1 in the above case [3]. Fixes: 81e9fe5a2988 ("arm: implement find_next_zero_bit function") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* | | | db410c: set clk node to be probed before relocationRamon Fried2018-05-082-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock node is used by the serial driver and it's needed before relocation. This patch ensures that the msm-serial driver can actually use the clock node. Signed-off-by: Ramon Fried <ramon.fried@linaro.org>
* | | | ARM: dts: sti: Add stih410-b2260-u-boot.dtsiPatrice Chotard2018-05-081-0/+16
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | STiH410 has 2 PHYs wired on the DWC3 IP, USB2 and USB3 PHYs. As currently no U-boot driver is available for the USB3 PHY and to avoid issue during DWC3 drive probe, we use DWC3 IP with only USB2 PHY using stih410-b2260-u-boot.dtsi file. Fixes: 2fd4242cc50e ("ubs: xhci-dwc3: Enable USB3 PHY when available") Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | | ARM: dts: stm32mp157: Add vrefbuf DT nodePatrice Chotard2018-05-081-0/+9
| | | | | | | | | | | | | | | | | | | | | Add vrefbuf device tree node. This allows to get a voltage reference for ADCs. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | | ARM: dts: stm32mp157c-ed1: Add regulator nodePatrice Chotard2018-05-081-0/+272
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add regulator nodes needed by stpmu1 regulator driver Add vmmc-supply and vqmmc-supply regulator property for sdmmc1 and sdmmc2. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | | ARM: dts: stm32mp157: Add SoC pwr regulator entryPatrice Chotard2018-05-081-0/+33
| | | | | | | | | | | | | | | | | | | | | Add SoC power regulator entry for reg11, reg18 and usb33 regulator. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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