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* Merge tag 'xilinx-for-v2021.10-rc3' of ↵WIP/27Aug2021Tom Rini2021-08-2719-38/+148
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.10-rc3 xilinx: - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY - Print information about cpu via soc drivers and enable DISPLAY_CPUINFO - Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT zynq: - Wire single QSPI - Use power-source instead of io-standard properties - Enable nor on zc770-xm012 zynqmp: - Change handling around multi_boot() - Setup offset for u-boot.itb in spi - Generate run time dfu_alt_info for capsule update - Use explicit values for enums (zynqmp_firmware.h) - Enable RTC/SHA1/BUTTON/BUTTON_GPIO command - Disable WDT driver by default - Bind usb/scsi via preboot because of EFI - DT updates/fixes - Add soc driver - Fix SPL SPI boot mode versal: - Add soc driver sdhci: - Update tap delay programming for zynq_sdhci driver cmd: - Fix RTC uclass handling in date command - Update pwm help message - Update reset help message watchdog: - Fix wwdt compilation rtc: - Deal with seq alias in rtc uclass - Add zynqmp RTC driver fdt: - Add kernel-doc for fdt_fixup_memory_banks()
| * xilinx: zynqmp: Update descriptions for u-boot.itsMichal Simek2021-08-261-2/+2
| | | | | | | | | | | | | | Use TF-A instead of ATF in description. And update generic description with removing ATF because also configurations without it are supported. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: common: Enabling generic function for DT reselectionMichal Simek2021-08-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot support board detection at run time and based on it change DT. This feature is implemented for SOM Kria platforms which contain two eeproms which contain information about SOM module and CC (Carrier card). Full U-Boot starts with minimal DT file defined by CONFIG_DEFAULT_DEVICE_TREE which is available in multi DTB fit image. It is using default setup of board_name variable initializaed to DEVICE_TREE which corresponds to CONFIG_DEFAULT_DEVICE_TREE option. When DTB_RESELECT is enabled board_detection() is called. Keep it your mind that this code is called before relocation. board_detection() is calling xilinx_read_eeprom() which fills board_info (xilinx_board_description) structure which are parsed in board_name_decode(). Based on DT configuration and amount of nvmemX aliases name of the board is composed by concatenating CONFIG_SYS_BOARD "-" <board_name> "-rev" <board_revision> "-" <cc_name> "-rev" <cc_revision>. If CC is not present or more are available it keeps going. When board name is composed and returned from board_name_decode() it is assigned to board_name variable which is used by board_fit_config_name_match() which is called via fdtdec_setup() when it goes over config options in multi dtb FIT image. From practical point of view multi DTB image is key point here which has to contain configs for detected combinations. Unfortunately as of now they have to be full DTBs and DTBOs are not supported. That's why configuration like: config_X { description = "zynqmp-board-cc"; fdt = "board", "cc"; }; needs to be squashed together with: fdtoverlay -o zynqmp-board-cc -i arch/arm/dts/zynqmp-board.dtb \ arch/arm/dts/zynqmp-cc.dtbo and only one dtb is in fit: config_X { description = "zynqmp-board-cc"; fdt = "board-cc"; }; For creating multi DTBs fit image use mkimage -E, e.g.: mkimage -E -f all.its all.dtb When DTB_RESELECT is enabled xilinx_read_eeprom() is called before relocation and it uses calloc for getting a buffer. Because this is dynamic memory it is not relocated that's why xilinx_read_eeprom() is called again as the part of board_init(). This second read with calloc buffer placed in proper position board_late_init_xilinx() can setup u-boot variables as before. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: Generate different u-boot.itb for MULTI_DTB_FITMichal Simek2021-08-261-0/+47
| | | | | | | | | | | | | | | | | | | | When MULTI_DTB_FIT is enabled fit-dtb.blob fit image is created which contain all DTBs listed by CONFIG_OF_LIST. And with DTB_RELESELECT there is a need to handle it as one file with DTBs in it not as separate DTBs in u-boot.its/itb. That's why extend mkimage_fit_atf.sh to generate u-boot.itb correctly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: dts: Make sure that all DTBs are 64bit alignedMichal Simek2021-08-261-1/+1
| | | | | | | | | | | | | | Start of DTB should be 64bit aligned that's why also make sure that end is also 64bit aligned. It is not required but it is nice thing to do. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * soc: xilinx: versal: Add soc_xilinx_versal driverT Karthik Reddy2021-08-263-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | soc_xilinx_versal driver allows identification of family & revision of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL. Probe this driver using platdata U_BOOT_DEVICE structure which is defined at mach-versal/cpu.c. Add this config to xilinx_versal_virt_defconfig & xilinx_versal_mini_ospi_defconfig file to select this driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driverT Karthik Reddy2021-08-263-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | soc_xilinx_zynqmp driver allows identification of family & revision of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP. Add this config to xilinx_zynqmp_virt_defconfig file. Probe this driver using platdata U_BOOT_DEVICE structure which is specified in mach-zynqmp/cpu.c. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Enable smcc and nor for zc770-xm012Michal Simek2021-08-261-0/+9
| | | | | | | | | | | | Enable cfi flash on zc770-xm012 configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Wire single qspi on couple of boardsMichal Simek2021-08-264-0/+32
| | | | | | | | | | | | Single configuration is working fine and no issue to enable it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Replace 'io-standard' with 'power-source' propertySai Krishna Potthuri2021-08-262-20/+20
| | | | | | | | | | | | | | | | Replace 'io-standard' property with 'power-source' property in all zynq dts files to be in sync with Zynq Pinctrl driver. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)Raju Kumar Pothuraju2021-08-264-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing "jedec, spi-nor" compatible string for QSPI flash node. Spi-nor framework uses this compatibility string to probe & initialize flash. With missing compatibility string we are observing below error: Zynq> sf probe 0 0 0 jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes: 00, 00, 00 Failed to initialize SPI flash at 0:0 (error -2) Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Update comment style sm-k26Michal Simek2021-08-261-1/+1
| | | | | | | | | | | | Trivial style patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Fix header alignment on kv260 boardsMichal Simek2021-08-262-8/+8
| | | | | | | | | | | | Fix header alignment. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Fix node name for ds35/36 ledsMichal Simek2021-08-261-2/+2
| | | | | | | | | | | | By dt-binding specs led nodes should have -led suffix that's why add it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm: socfpga: Enable Intel N5X device buildSiew Chin Lim2021-08-252-6/+43
| | | | | | | | | | | | Add defconfig for N5X to support legacy, ATF and VAB boot flow. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: dts: Add base dtsi and devkit dts for Intel N5X deviceSiew Chin Lim2021-08-254-0/+377
| | | | | | | | | | | | | | | | Add device tree for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
* | arm: socfpga: Add SPL for Intel N5X deviceSiew Chin Lim2021-08-251-0/+94
| | | | | | | | | | | | Add SPL for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee2021-08-252-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* | arm: socfpga: Changed misc_s10.c to misc_soc64.cSiew Chin Lim2021-08-252-8/+8
| | | | | | | | | | | | | | Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: Add clock manager for Intel N5X deviceSiew Chin Lim2021-08-253-0/+94
| | | | | | | | | | | | Add clock manager for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.hSiew Chin Lim2021-08-255-5/+1
| | | | | | | | | | | | | | Move cm_get_mpu_clk_hz function declaration from individual device's clock manager header file to common clock_manager.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: Get clock manager base address for Intel N5X deviceSiew Chin Lim2021-08-251-0/+3
| | | | | | | | | | | | Add N5X clock manager to socfpga_get_managers_addr function. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: Add handoff data support for Intel N5X deviceTien Fong Chee2021-08-243-48/+140
| | | | | | | | | | | | | | | | | | N5X support both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and N5X device. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* | arm: socfpga: Add base address for Intel N5X deviceSiew Chin Lim2021-08-241-1/+2
| | | | | | | | | | | | | | Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.hSiew Chin Lim2021-08-241-4/+4
| | | | | | | | | | | | | | Rename to common file name to used by all SOC64 devices and change "_S10_" to "_SOC64_" in base_addr_soc64.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux ↵Siew Chin Lim2021-08-241-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | function Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when OS booted from FIT image for Stratix 10 and Agilex. This flow is common for all Intel SOC64 devices. U-Boot will update 'fdt_addr' environment value based on FIT image in board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr' environment value to retrieve the device tree node. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | armv8: fsl : create bootcmd and mcinitcmd as per boot sourceWasim Khan2021-08-181-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | NXP platforms expect custom bootcmd and mcinitcmd to be updated as per boot source with default environment. Check env variable fsl_bootcmd_mcinitcmd_set to prepare bootcmd and mcinitcmd Fixes: cbf77d201870 (armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A) Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | board: sl28: drop unneeded and outdated flash partitionsMichael Walle2021-08-181-55/+0
| | | | | | | | | | | | | | | | | | This board doesn't use the MTD subsystem in u-boot, thus there is no need to specify the partitions. They are outdated anyway. Just drop them. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | arm: Finish migration of HAS_FSL_XHCI_USBTom Rini2021-08-181-2/+4
| | | | | | | | | | | | | | | | This symbol was largely migrated, except for one case. Update it. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | arm: stm32mp1: Implement ECDSA signature verificationAlexandru Gagniuc2021-08-163-0/+112
| | | | | | | | | | | | | | | | The STM32MP ROM provides several service. One of them is the ability to verify ecdsa256 signatures. Hook the ROM API into the ECDSA uclass. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* | ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHzMarek Vasut2021-08-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, which causes additional signal delay. At 108 MHz, this delay triggers a sporadic issue where the first bit of RX data is not received by the QSPI controller. There are two options of addressing this problem, either by using the DLYB block to compensate the extra delay, or by reducing the QSPI bus clock frequency. The former requires calibration and that is overly complex for SPL, so opt for the second option. This incurs 20ms delay during boot, when SPL loads U-Boot to DRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | arm: dts: stm32mp15: alignment with v5.14Patrick Delaunay2021-08-163-9/+42
| | | | | | | | | | | | | | | | | | | | | | Device tree alignment with Linux kernel v5.14-rc3 - ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15 - ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151 - ARM: dts: stm32: add a new DCMI pins group on stm32mp15 - ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | stm32mp: correctly handle board_get_usable_ram_top(0)Patrick Delaunay2021-08-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function board_get_usable_ram_top can be called after relocation with total_size = 0 to get the uppermost pointer that is valid to access in U-Boot. When total_size = 0, the reserved memory should be not take in account with lmb library and 'gd->ram_base + gd->ram_size' can be used. It is the case today in lib/efi_loader/efi_memory.c:efi_add_known_memory() and this patch avoids that the reserved memory for OP-TEE is not part of the EFI available memory regions. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | stm32mp1: stm32prog: remove stm32prog_get_tee_partitions with FIPPatrick Delaunay2021-08-164-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | The MTD tee partitions used to save the OP-TEE binary are needed when TF-A doesn't use the FIP container to load binaries. This patch puts under CONFIG_STM32MP15x_STM32IMAGE flag the associated code in U-Boot binary and prepare the code cleanup when CONFIG_STM32MP15x_STM32IMAGE support will be removed after TF-A migration to FIP support. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | arm: stm32mp: add defconfig for trusted boot with FIPPatrick Delaunay2021-08-162-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TF-A FIP support for trusted boot on STM32MP15x, when STM32MP15x_STM32IMAGE is not activated. With FIP support the SSBL partition is named "fip" and its size is 4MB, so the ENV partition name in device tree (for SD card or eMMC) or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_REDUND) need to be modified. With FIP the TEE MTD partitions are removed because the OP-TEE binray are included in the FIP containers. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | arm: stm32mp: handle the OP-TEE nodes in DT with FIP supportPatrick Delaunay2021-08-163-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With FIP support in TF-A (when CONFIG_STM32MP15x_STM32IMAGE is not activated), the DT nodes needed by OP-TEE are added by OP-TEE firmware in U-Boot device tree, present in FIP. These nodes are only required in trusted boot, when TF-A load the file u-boot.stm32, including the U-Boot device tree with STM32IMAGE header, in this case OP-TEE can't update the U-Boot device tree. Moreover in trusted boot mode with FIP, as the OP-TEE nodes are present in U-Boot device tree only when needed the function stm32_fdt_disable_optee can be removed. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | arm: stm32mp: add config for STM32IMAGE supportPatrick Delaunay2021-08-162-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default for trusted boot with TF-A, U-Boot (u-boot-nodtb) is located in FIP container with its device tree and with the secure monitor (provided by TF-A or OP-TEE). The FIP file is loaded by TF-A BL2 and each components is extracted at the final location. This patch add CONFIG_STM32MP15x_STM32IMAGE to request the STM32 image generation for SOC STM32MP15x when FIP container is not used (u-boot.stm32 is loaded by TF-A as done previously to keep the backward compatibility). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | Merge tag 'u-boot-rockchip-20210812' of ↵Tom Rini2021-08-1252-1203/+2216
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add Rockchip SFC driver support; - DTS sync from kernel; - emmc hs400 support for rk3399; - Fix for spinore bootdevice and MMC boot order;
| * | rockchip: px30: add support for SFC for Odroid Go AdvanceChris Morgan2021-08-122-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Odroid Go Advance uses a Rockchip Serial Flash Controller with an XT25F128B SPI NOR flash chip. This adds support for both. Note that while both the controller and chip support quad mode, only two lines are connected to the chip. Changing the pinctrl to bus2 and setting tx and rx lines to 2 for this reason. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: px30: add the serial flash controllerChris Morgan2021-08-121-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | Add the serial flash controller to the devicetree for the PX30. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: px30: Add support for using SFCChris Morgan2021-08-121-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for setting the correct pin configuration for the Rockchip Serial Flash Controller found on the PX30. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: Fix u-boot-rockchip.bin buildJohan Gunnarsson2021-08-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are a few arm32 rockchip board configs that don't generate u-boot-rockchip.bin when running make because CONFIG_BINMAN is not enabled. This patch changes CONFIG_ARCH_ROCKCHIP to also select CONFIG_BINMAN if CONFIG_SPL and !CONFIG_ARM64. Example builds that don't generate u-boot-rockchip.bin without this patch: export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make kylin-rk3036_defconfig make export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make rock_defconfig make export ARCH=arm export CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf- make tinker-rk3288_defconfig make Signed-off-by: Johan Gunnarsson <johan.gunnarsson@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: dts: sync the Rockhip 3368 SoCs from LinuxPeter Robinson2021-08-125-220/+118
| | | | | | | | | | | | | | | | | | | | | Sync the rk3368 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: dts: sync the Rockhip 3328 SoCs from LinuxPeter Robinson2021-08-1210-258/+487
| | | | | | | | | | | | | | | | | | | | | Sync the rk3328 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm: dts: sync the Rockhip 3399 SoCs from LinuxPeter Robinson2021-08-1225-447/+871
| | | | | | | | | | | | | | | | | | | | | | | | Sync the rk3399 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> (Remove the conflict content for vmarc-som) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm64: rk3399: r4s: Remove undesirable MAC address fetching methods for ethernetXiaobo Tian2021-08-111-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the recommended MAC address from the network card. NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which stores the MAC address. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm64: rk3399: r4s: Inheritance uses the sdmmc definition in dtsiXiaobo Tian2021-08-111-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | The host-index-min property is invalid, so it inherits from the sdmmc definition in dtsi. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm64: rk3399: r4s: correct the LEDS label nameXiaobo Tian2021-08-111-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Correct the LEDS label name and remove the board type prefix, which is actually unnecessary here, removes the redefined system status LED pin. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | ARM: dts: rockchip: update rk3188-radxarock.dtsJohan Jonker2021-08-112-53/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | ARM: dts: rockchip: update rk3188.dtsiJohan Jonker2021-08-112-136/+356
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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