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* efi_loader: Rename EFI_RUNTIME_{TEXT, DATA} to __efi_runtime{, _data}Alexander Graf2016-10-191-6/+6
| | | | | | | | | | | Compiler attributes are more commonly __foo style tags rather than big upper case eye sores like EFI_RUNTIME_TEXT. Simon Glass felt quite strongly about this, so this patch converts our existing defines over to more eye friendly ones. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* efi_loader: Add generic PSCI RTSAlexander Graf2016-10-191-5/+26
| | | | | | | | | Now that we have generic PSCI reset and shutdown support in place, we can advertise those as EFI Run Time Services, allowing efi applications and OSs to reset and shut down systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Provide common PSCI based reset handlerAlexander Graf2016-10-192-0/+25
| | | | | | | | | | | | | | | | Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. On these systems, we do not need to implement system reset manually, but can instead rely on higher level firmware to deal with it. The exclude list seems excessive right now, but NXP is working on providing an in-tree PSCI implementation, so that all NXP systems can eventually use PSCI as well. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: fix meson] Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Add PSCI shutdown functionAlexander Graf2016-10-182-0/+16
| | | | | | | | | Using PSCI you can not only reset the system, you can also shut it down! This patch exposes a function to do exactly that to whatever code wants to make use of it. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Disable HVC PSCI calls by defaultAlexander Graf2016-10-183-14/+13
| | | | | | | | | | | | | All systems that are running on armv8 are running bare metal with firmware that implements PSCI running in EL3. That means we don't really need to expose the hypercall variants of them. This patch leaves the code in, but makes the code explicit enough to have the compiler optimize it out. With this we don't need to worry about hvc vs smc calling convention when calling psci helper functions. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: create .secure_stack section only for PSCIMasahiro Yamada2016-10-141-2/+5
| | | | | | | | | | | | | | | Jon Master reports that QEMU refuses to load a U-Boot image built with CONFIG_ARMV7_NONSEC, but without CONFIG_ARMV7_PSCI since commit 5a3aae68c74e ("ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI"). It looks like only PSCI that needs the Secure stack, so move the #ifdef to guard the whole of .secure_stack allocation in order not to create the empty section. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Jon Masters <jcm@redhat.com> Link: http://patchwork.ozlabs.org/patch/664025/
* libfdt: Sync fdt_for_each_subnode() with upstreamSimon Glass2016-10-131-2/+2
| | | | | | | | | | | The signature for this macro has changed. Bring in the upstream version and adjust U-Boot's usages to suit. Signed-off-by: Simon Glass <sjg@chromium.org> Update to drivers/power/pmic/palmas.c: Signed-off-by: Keerthy <j-keerthy@ti.com> Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
* libfdt: Bring in upstream stringlist functionsSimon Glass2016-10-132-10/+9
| | | | | | | | | | | | | | These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-10-122-43/+76
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| * ARM: tegra: reduce DRAM size mapped into MMU on ARM64Stephen Warren2016-10-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM CPUs can architecturally (speculatively) prefetch completely arbitrary normal memory locations, as defined by the current translation tables. The current MMU configuration for 64-bit Tegras maps an extremely large range of addresses as DRAM, well beyond the actual physical maximum DRAM window, even though U-Boot only needs access to the first 2GB of DRAM; the Tegra port of U-Boot deliberately limits itself to 2GB of RAM since some HW modules on at least some 64-bit Tegra SoCs can only access a 32-bit physical address space. This change reduces the amount of RAM mapped via the MMU to disallow the CPU from ever speculatively accessing RAM that U-Boot will definitely not access. This avoids the possibility of the HW raising SError due to accesses to always-invalid physical addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * colibri_t20: fix usb operation and controller orderMarcel Ziswiler2016-10-101-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch the following error will be shown: Colibri T20 # usb start starting USB... No controllers found This patch fixes USB operation and also the controller order as the CI UDC driver may only be instantiated on the first aka OTG port. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * colibri_t20: fix display configurationMarcel Ziswiler2016-10-101-20/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch the following error will be shown: stdio_add_devices: Video device failed (ret=-22) As commit ec5507707a1d1e84056a6c864338f95f6118d3ca (video: tegra: Move to using simple-panel and pwm-backlight) states the Colibri T20 needs updating too which this patch finally attempts doing. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-10-121-21/+43
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| * | sunxi: Fix H3 DRAM impedance calibration on rev. A chipsJens Kuske2016-10-101-21/+43
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H3 seems to have a silicon bug breaking the impedance calibration. This is currently worked around in software by multiple steps combining the results to replace the wrong values. Revision A chips need a different workaround, which is present in the vendor bootloader too, but got overlooked in lack of information and affected boards till now. This commit adds a simplified version without correction factor, which would be 1.00 for all known boards anyway. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-10-128-337/+372
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| * | reset: uniphier: add reset controller driver for UniPhier SoCsMasahiro Yamada2016-10-101-0/+1
| | | | | | | | | | | | | | | | | | | | | This is the initial commit for UniPhier reset controller driver. Most code was ported from Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: insert udelay() just before support_card_reset_deassert()Masahiro Yamada2016-10-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As for LD11/LD20, we can no longer rely on the udelay() in the PLL init functions. udelay(200) is needed here to keep the ethernet device in the reset state for enough time. Anyway, 200 usec is quite short for humans, so nobody cares it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add work-around for VBO noise problemMasahiro Yamada2016-10-101-0/+7
| | | | | | | | | | | | | | | | | | | | | Raise the VDD09 voltage line to 1.0V to suppress VBO noise. This errata work-around code is needed only for ES1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: update DRAM init code for LD20 SoC (2nd)Masahiro Yamada2016-10-102-333/+356
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Do not reference CONFIG_DDR_FREQ; now the DDR frequency is passed from the uniphier_board_data structure - Constify parameter arrays - Tidy up cluttered macros - Lots of code cleanups - Lots of coding style fixes Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: enable SSC for DPLL (DRAM PLL) on LD11 SoCMasahiro Yamada2016-10-101-0/+1
| | | | | | | | | | | | | | | | | | For Electro-Magnetic Compatibility test. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: do not setup pins for System Bus on NAND boot modeMasahiro Yamada2016-10-102-2/+6
| |/ | | | | | | | | | | | | | | | | For LD11 and LD20 SoCs, the System Bus and NAND are multiplexed in the same I/O pins. When booting from a NAND device, pin-mux for the System Bus must not be set-up because they are exclusive with each other. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-10-121-0/+4
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| * | arm: kirkwood: add support for Synology DS109 boardWalter Schweizer2016-10-091-0/+4
| |/ | | | | | | | | | | | | | | | | Synology DS109 is based on MV88F6281. The code is based on Dreamplug code with modificatons from Synologys open source repository. Signed-off-by: Walter Schweizer <swwa@users.sourceforge.net> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-10-1216-58/+338
|\ \ | |/ |/| | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: include/configs/ls1021aqds.h include/configs/ls1021atwr.h
| * armv8: ls2080a: Add USB node in dts for ls2080aSriram Dash2016-10-071-0/+14
| | | | | | | | | | | | | | | | Add the USB node for LS2080a in dts. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> [York Sun: replace ls2080 with ls2080a in commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: ls1021a: Move DDR config options to KconfigYork Sun2016-10-062-10/+47
| | | | | | | | | | | | | | | | Move DDR3, DDR4 and related config options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * armv8: fsl-layerscape: Move DDR config options to KconfigYork Sun2016-10-062-14/+54
| | | | | | | | | | | | | | | | Move DDR3, DDR4 and realted options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to KconfigYork Sun2016-10-064-7/+27
| | | | | | | | | | | | | | Move these options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to KconfigYork Sun2016-10-062-3/+8
| | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. NUM_DDR_CONTROLLERS is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move SYS_FSL_IFC_BANK_COUNT to KconfigYork Sun2016-10-063-3/+12
| | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. This option is also used by PowerPC SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move MAX_CPUS to KconfigYork Sun2016-10-064-5/+24
| | | | | | | | | | | | | | | | Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Move FSL_LSCH2 FSL_LSCH3 to KconfigYork Sun2016-10-063-0/+27
| | | | | | | | | | | | | | | | Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * arm: Fix Kconfig for proper display menuYork Sun2016-10-062-6/+10
| | | | | | | | | | | | | | | | Some config options should not have prompt. They are selected by choosing target. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * armv8: fsl: Enable USB only when SYSCLK is 100 MHzSriram Dash2016-10-061-0/+20
| | | | | | | | | | | | | | | | SYSCLK is used as a reference clock for USB. When the USB controller is used, SYSCLK must meet the additional requirement of 100 MHz. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1043: Add USB node in dts for ls1043Sriram Dash2016-10-061-0/+21
| | | | | | | | | | | | | | Add the USB node for LS1043 in dts. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539Hou Zhiqiang2016-10-063-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * ARMv7: LS102xA: Move two macros from header files to KconfigHongbo Zhang2016-10-061-0/+4
| | | | | | | | | | | | | | | | | | | | Following commits 217f92b and 1544698, these two config CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are moved to Kconfig, for correctly select ARMV7_PSCI. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Fix "cpu status" commandYork Sun2016-10-063-4/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The core position is not continuous for some SoCs. For example, valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some registers (including boot release register) only count existing cores. Current implementation of cpu_mask() complies with the continuous numbering. However, command "cpu status" queries the spin table with actual core position. Add functions to calculate core position from core number, to correctly calculate offsets. Tested on LS2080ARDB and LS1043ARDB. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8/fsl-layerscape: print SoC revsion numberWenbin Song2016-10-061-0/+3
| | | | | | | | | | | | | | | | The exact SoC revsion number can be recognized from U-Boot log. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: LS1021a: enable i-cache in start.SXiaoliang Yang2016-10-062-1/+5
| | | | | | | | | | | | | | | | | | | | Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First stage of u-boot can run faster after that. There is a description about skip lowlevel init in board/freescale/ls1021atwr/README. Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-lsch2: enable snoopable sata read and writeTang Yuantian2016-10-063-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-lsch2: adjust sata parameterTang Yuantian2016-10-062-4/+0
| | | | | | | | | | | | | | | | The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-10-0829-64/+5482
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| * | ARM: vf610: use strcpy for soc environment variableStefan Agner2016-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To create the soc environment variable we concatenate two strings on the stack. So far, strcat has been used for the first string as well as for the second string. Since the variable on the stack is not initialized, the first strcat may not start using the first entry in the character array. This then could lead to an buffer overflow on the stack. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| * | arm: dts: imx7: add Ricoh RN5T567 PMIC nodeStefan Agner2016-10-071-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add device tree node for Ricoh RN5T567. Currently we do not need the individual DC/DC converters or LDO's (and they are also not yet supported by the driver). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | arm: dts: imx7: add basic i.MX 7/Colibri iMX7 device treeStefan Agner2016-10-073-0/+288
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add base device for NXP i.MX 7Solo/7Dual. The two SoC are very similar and hence can share the same device tree for boot loaders purpose. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | arm: dts: imx7: add pinctrl definesStefan Agner2016-10-071-0/+1151
| | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl defines for NXP i.MX 7Solo/7Dual SoC. The pinctrl format is compatible to the Linux kernel, hence this file is a simple copy from the Linux kernel (commit 97f5c1817b7e). Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| * | pcm052: add new BK4r1 target based on PCM052 SoMAlbert ARIBAUD \(3ADEV\)2016-10-064-2/+57
| | | | | | | | | | | | Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | tools: mkimage: add support for Vybrid image formatAlbert ARIBAUD \(3ADEV\)2016-10-062-0/+8
| | | | | | | | | | | | | | | | | | | | | This format can be flashed directly at address 0 of the NAND FLASH, as it contains all necessary headers. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | imx: imx6ul: disable POR_B internal pull upPeng Fan2016-10-041-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From TO1.1, SNVS adds internal pull up control for POR_B, the register filed is GPBIT[1:0], after system boot up, it can be set to 2b'01 to disable internal pull up. It can save about 30uA power in SNVS mode. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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