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* imx: mkimage: add size check to the u-boot.imx make targetMarcel Ziswiler2018-11-121-0/+16
| | | | | | | | | | | | The make macro to check if the binary exceeds the board size limit is taken straight from the root Makefile. Without this and e.g. enabled EFI Vybrid fails booting as the regular size limit check does not take the final u-boot.imx binary size into account which is bigger due to alignment as well as IMX header stuff. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* imx: imx6: perform gpr_init only on suitable cpu typesChristoph Niedermaier2018-11-081-0/+8
| | | | | | | | | If the function gpr_init is used in a common MX6 spl implementation we have to ensure that it is only called for suitable cpu types, otherwise it breaks hardware parts like enet1, can1, can2, etc. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.de>
* Merge tag 'u-boot-imx-20181106' of git://git.denx.de/u-boot-imxTom Rini2018-11-061-12/+8
|\ | | | | | | Fix coverity issues for i.MX8
| * ARM: dts: fsl-imx8qxp-mek: Move regulator outside "simple-bus"Fabio Estevam2018-11-061-12/+8
| | | | | | | | | | | | | | | | | | | | Commit 3c28576bb0f0 ("arm: dts: imx8qxp: fix build warining") fixed the dts warning by removing the unnecessary #address-cells/#size-cells, but the recommendation for regulators is not to place them under "simple-bus", so move the reg_usdhc2_vmmc regulator accordingly. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* | arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGAStefan Roese2018-11-061-2/+2
| | | | | | | | | | | | | | | | | | The new board version has the 2nd FPGA connected via CS# 0 instead of 2 on SPI bus 1. Change this setup in the DT accordingly. Please note that this change does still work on the old board version because the CS signal is not used on this board. Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: armada-xp-theadorable.dts: Add "spi-flash" compatible propertyStefan Roese2018-11-061-1/+1
| | | | | | | | | | | | | | Add the "spi-flash" compatible string so that the generic sf_probe driver can probe the SPI flash on the theadorable Armada-XP board. Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: Move PCI(e) MBUS window to end of RAMStefan Roese2018-11-062-5/+9
|/ | | | | | | | | | | | | | | | | | | | | With patch 49b23e035d96 (pci: mvebu: Increase size of PCIe default mapping) the mapping size for each PCI(e) controller was increased from 32MiB to 128MiB. This leads to problems on boards with multiple PCIe slots / ports which are unable to map all PCIe ports, e.g. the Armada-XP theadorable: DRAM: 2 GiB (667 MHz, 64-bit, ECC not enabled) SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB Cannot add window '4:f8', conflicts with another window PCIe unable to add mbus window for mem at f0000000+08000000 Model: Marvell Armada XP theadorable This patch moves the base address for the PCI(e) memory spaces from 0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now). This gives move room and flexibility for PCI(e) mappings. Signed-off-by: Stefan Roese <sr@denx.de> Cc: VlaoMao <vlaomao@gmail.com> Tested-by: VlaoMao <vlaomao at gmail.com>
* ARM: rmobile: Generate fitting mem_map on Gen3Marek Vasut2018-11-022-1/+91
| | | | | | | | | | | | | | | Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire 64bit DRAM space as cachable. On CortexA57, this might result in odd side effects, where the CPU tries to prefetch from those areas and if there is no DRAM backing them, CPU bus hang can happen. This patch fixes it by generating the mem_map structure based on the actual memory layout obtained from the DT, thus not marking areas without any DRAM behind them as cachable. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Fixes: c1ec34763811d ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3") Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* arm: socfpga: imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITIONSimon Goldschmidt2018-10-311-1/+1
| | | | | | | | Using imply for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION instead of select ensures we can build without partition support (used to build a network boot only version of SPL and U-Boot). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-10-295-9/+35
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| * sunxi: store DRAM size in SPL headerAndre Przywara2018-10-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we rely on the infamous get_ram_size() function to learn the actual DRAM size in U-Boot proper. This function has two issues: 1) It only works if the DRAM size is a power of two. We start to see boards which have 3GB of (usable) DRAM, so this does not fit anymore. 2) As U-Boot has no notion of reserved memory so far, it will happily ride through the DRAM, possibly stepping on secure-only memory. This could be a region of DRAM reserved for OP-TEE or some other secure payload, for instance. It will most likely crash in that case. As the SPL DRAM init routine has very accurate knowledge of the actual DRAM size, lets propagate this wisdom to U-Boot proper. We re-purpose a currently reserved word in our SPL header for that. The SPL itself stores the detected DRAM size there, and bumps the SPL header version number in that case. U-Boot proper checks for a valid SPL header and a high enough version number, then uses the DRAM size from there. If the SPL header field is not sufficient, we fall back to the old DRAM scanning routine. Part of the DRAM might be present and probed by SPL, but not accessible by the CPU. They're restricted in the main U-Boot binary, when accessing the DRAM size from SPL header. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: add Kconfig option for the maximum accessible DRAMIcenowy Zheng2018-10-291-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is accessible. Add a Kconfig option for the maximum accessible DRAM. For A80 it should be a much higher value (8GiB), but as I have no A80 device to test and originally U-Boot only supports 2GiB DRAM on A80, it currently still falls under the 2GiB situation. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: map DRAM part with 3G sizeIcenowy Zheng2018-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | All Allwinner 64-bit SoCs now are known to be able to access 3GiB of external DRAM, however the size of DRAM part in the MMU translation table is still 2GiB. Change the size of DRAM part in MMU table to 3GiB. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Extend SPL header versioningAndre Przywara2018-10-291-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Allwinner SoCs we use some free bytes at the beginning of the SPL image to store various information. We have a version byte to allow updates, but changing this always requires all tools to be updated as well. Introduce the concept of semantic versioning [1] to the SPL header: The major part of the version number only changes on incompatible updates, a minor number bump indicates backward compatibility. This patch just documents the major/minor split, adds some comments to the header file and uses the versioning information for the existing users. [1] https://semver.org Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
| * sunxi: disable Pine A64 model detection code on other boardsIcenowy Zheng2018-10-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Pine A64 Plus/non-Plus model detection code is now built on all 64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is in use. Disable them when the board is Pine A64 by adding a Kconfig option that is only selected on Pine A64. On GCC 7.3.1 this makes the size of the function reduces 184 bytes, and saves a 104 byte strstr() function, then makes SPL on H6 succeed to build. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * sunxi: Fix typos of spelling AllwinnerPriit Laes2018-10-242-2/+2
| | | | | | | | | | | | Signed-off-by: Priit Laes <plaes@plaes.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imxTom Rini2018-10-2543-12/+2631
|\ \ | |/ |/| | | Merged imx8 architecture, fix build for imx8 + warnings
| * arm: dts: imx8qxp: fix build wariningPeng Fan2018-10-251-2/+0
| | | | | | | | | | | | | | | | | | | | Fix below build warning. arch/arm/dts/fsl-imx8qxp-mek.dtb: Warning (avoid_unnecessary_addr_size): /regulators: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mkimage: avoid stop CI when required files not existsPeng Fan2018-10-251-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | Introduce a new script to check whether file exists and use that check in Makefile to avoid break CI system. The script return 1 when the required files not exists, return 0 when files exists. The script will ignore check to u-boot-dtb.bin, because if there is something wrong to generate u-boot-dtb.bin, there must be some code error. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7: avoid some initialization if low level is skippedRui Miguel Silva2018-10-222-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can have the case where u-boot is launched after some other low level enabler, like for example when u-boot runs after arm-trusted-firmware and/or optee. So, because of that we may need to jump the initialization of some IP blocks even because we may no longer have the permission for that. So, if the config option to skip low level init is set disable also timer, board and csu initialization. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Peng Fan <peng.fan@nxp.com> Cc: u-boot@lists.denx.de Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx: include imx8image supportPeng Fan2018-10-221-6/+11
| | | | | | | | | | | | | | | | | | When building i.MX8/8X board, use imx8image type. `-e $(CONFIG_SYS_TEXT_BASE)` is not needed, but no harm to keep it for i.MX8/8X Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: add i.MX8QXP MEK board supportPeng Fan2018-10-223-0/+261
| | | | | | | | | | | | | | | | | | | | | | Add i.MX8QXP MEK board support Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver. Added README file. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
| * arm: dts: introduce dtsi for i.MX8QXPPeng Fan2018-10-224-0/+627
| | | | | | | | | | | | | | | | Introduce dtsi for i.MX8QXP, since there is other variants i.MX8DX(P), so add them there, because i.MX8QXP includes the dtsi of them. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
| * power: Add power domain driver for i.MX8Peng Fan2018-10-221-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the power domain DM driver for i.MX8, that it depends on the DTB power domain trees to generate the power domain provider devices. Users need to add power domain trees with property "compatible = "nxp,imx8-pd";" When power on a PD device, the driver will power on its ancestor PD devices in power domain tree. When power off a PD device, the driver will check its child PD devices first. Only if all child PD devices are off, then power off the current PD device. Then the driver checks sibling PD devices. If sibling PD devices are off, then it will power off parent PD device. There is no counter maintained in this driver, but a state to hold current on/off state. So the request and free functions are empty. The power domain implementation in i.MX8 DTB set the "#power-domain-cells" to 0, so there is no ID binding with each PD device. We don't use "id" variable in struct power_domain. At the same time, we have to set of_xlate to empty to bypass standard of_xlate in uclass driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * gpio: mxc_gpio: add support for i.MX8Peng Fan2018-10-221-0/+21
| | | | | | | | | | | | | | | | Add i.MX8 support, there are 8 GPIO banks. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: add dummy clockPeng Fan2018-10-222-0/+48
| | | | | | | | | | | | | | | | | | This driver is mostly used to avoid build errors. We use uclass clk driver for clk related operations. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: add iomux configuration apiPeng Fan2018-10-223-1/+84
| | | | | | | | | | | | | | | | Add iomux configuration api. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: cpu: add uclass based CPU driverAnatolij Gustschin2018-10-222-78/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | print_cpuinfo() in board init code requires uclass CPU driver, add it to be able to display CPU info when CONFIG_DISPLAY_CPUINFO option is enabled. CPU node in DT will have to include 'clocks' and 'u-boot,dm-pre-reloc' properties for generic print_cpuinfo() to work as expected. The driver outputs info for i.MX8QXP Rev A and Rev B CPUs. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * imx8: cpu: add function for reading FEC MAC from fuseAnatolij Gustschin2018-10-221-0/+38
| | | | | | | | | | | | | | | | | | FEC driver requires imx_get_mac_from_fuse(). Add it in preparation for ENETx support. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * imx8: add arch_cpu_init arch_cpu_init_dmPeng Fan2018-10-222-1/+61
| | | | | | | | | | | | | | | | Add arch_cpu_init(_dm) mainly to open the channel between ACore and SCU. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: add mmu and dram related functionsPeng Fan2018-10-221-0/+284
| | | | | | | | | | | | | | | | | | | | | | | | Add mmu memmap, some memory regions are reserved by M4, Arm Trusted Firmware, so need to get memreg using SCFW API and setup the memmap. Add dram_init, dram_init_banksize, get_effective_memsize functions, according to the memreg. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: implement mmc_get_env_devPeng Fan2018-10-221-0/+32
| | | | | | | | | | | | | | | | Implement mmc_get_env_dev for i.MX8. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: add boot device detectionPeng Fan2018-10-222-0/+95
| | | | | | | | | | | | | | | | | | Add get_boot_device to detect boot device. Add print_bootinfo to print the boot device info. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: add basic cpu supportPeng Fan2018-10-222-0/+100
| | | | | | | | | | | | | | | | | | Add basic cpu support, including cpu revision, cpu type, cpu core detection. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * armv8: add cpu core helper functionsPeng Fan2018-10-221-0/+26
| | | | | | | | | | | | | | | | Add helper functions to identify different armv8 variants. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx: add i.MX8 cpu typePeng Fan2018-10-222-0/+8
| | | | | | | | | | | | | | Add i.MX8 cpu type and is_imx8/is_imx8qxp help macros. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: pins: include i.MX8QXP pin header when CONFIG_IMX8QXP definedPeng Fan2018-10-221-0/+15
| | | | | | | | | | | | | | | | | | Include i.MX8QXP pin header when CONFIG_IMX8QXP defined, if no SoC macro defined, report error. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: add imx-regs header filePeng Fan2018-10-221-0/+46
| | | | | | | | | | | | | | | | Add imx-regs header file to include the register base definition Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx: boot_mode: Add FLEXSPI boot entryPeng Fan2018-10-221-0/+1
| | | | | | | | | | | | | | | | i.MX8 support FLEXSPI boot support. So add FLEXSPI boot entry. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * misc: imx8: add scfw api impementationPeng Fan2018-10-221-0/+30
| | | | | | | | | | | | | | | | | | | | Add clk/misc/pad/pm/rm scfw api implementaion for different drivers to invoke. The low level code is using misc_call to invoke imx8_scu driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * arm: global_data: add scu_dev for i.MX8Peng Fan2018-10-221-0/+4
| | | | | | | | | | | | | | | | | | Add scu_dev for i.MX8, this will be used as a handle to communite with SCU from A35. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * arm: build mach-imx for i.MX8Peng Fan2018-10-221-1/+1
| | | | | | | | | | | | | | | | Build mach-imx for i.MX8 Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx: add Kconfig entry for i.MX8QXPPeng Fan2018-10-223-0/+22
| | | | | | | | | | | | | | | | Add Kconfig entry for i.MX8QXP Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * imx8: add scfw macro definitionPeng Fan2018-10-227-0/+636
| | | | | | | | | | | | | | | | Add SCFW macro definition. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * arm: mx5: Add M53Menlo boardMarek Vasut2018-10-161-0/+6
| | | | | | | | | | | | | | | | Add Menlosystems M53 board, based on the M53 SoM. This board has Ethernet, USB host, USB gadget, UART and LCD on it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * arm: mx5: Add LDB clock config codeMarek Vasut2018-10-162-0/+30
| | | | | | | | | | | | | | | | Add code to configure PLL4, from which the LDB clock are directly derived. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * arm: imx: mx5: Make videoskip available on MX5Marek Vasut2018-10-161-1/+3
| | | | | | | | | | | | | | | | | | The board_video_skip() implementation in imx-common/video.c works on i.MX5x as well, so loosen the SoC filter in Makefile to make it available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * ARM: opos6ul: make the board boot againSébastien Szymanski2018-10-094-4/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9faa43c4b5e5 ("ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl") removes the u-boot,dm-spl properties from the imx6ul.dtsi file and breaks the OPOS6UL board. Add the u-boot,dm-spl properties into *-u-boot.dts files to make the board boot again. Fixes: commit 9faa43c4b5e5 ("ARM: dts: i.MX6UL: U-Boot specific dts for u-boot, dm-spl") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx: mx7: fix potential overflow in imx_ddr_size()Marcel Ziswiler2018-10-091-0/+4
| | | | | | | | | | | | | | | | | | The imx_ddr_size() function may overflow as it is possible to kind of over provision the DDR controller. Fix this by capping it to 2 GB which is the maximum allowed size as per reference manual. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* | watchdog: aspeed: restore default value of reset_maskCédric Le Goater2018-10-221-0/+9
| | | | | | | | | | | | | | | | This is required for the current Linux kernel to reboot. It should also probably be fixed in Linux. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Simon Glass <sjg@chromium.org>
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