summaryrefslogtreecommitdiff
path: root/arch/arm/mach-imx
Commit message (Collapse)AuthorAgeFilesLines
* pci: Drop DM_PCISimon Glass2021-09-131-1/+1
| | | | | | This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'u-boot-imx-20210809' of ↵Tom Rini2021-08-0924-68/+3507
|\ | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210809 - new SOC: add support for imx8ulp - Toradex fixes for colibri (vf / imx6 / imx7 / imx8x) - convert to DM for mx28evk - Fixes for Gateworks ventana boards CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8639
| * imx: cmd: use struct cmd_tblPeng Fan2021-08-092-2/+2
| | | | | | | | | | | | cmd_tbl_t is removed, need use struct cmd_tbl Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx: add i.MX8ULP EVK supportPeng Fan2021-08-091-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8ulp: add upower api supportPeng Fan2021-08-095-0/+933
| | | | | | | | | | | | | | Add upower api support, this is modified from upower firmware exported package. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8ulp: Add workaround for eMMC bootYe Li2021-08-092-0/+17
| | | | | | | | | | | | | | | | | | | | | | When booting from boot part1/2, the image offset should be 0, but ROM has a bug to return 0x8000. Has to workaround the issue before ROM fix it. Use a ROM function to know boot from emmc boot part or user part So we can set the image offset accordingly. Signed-off-by: Ye Li <ye.li@nxp.com>
| * imx8ulp: Use DGO_GP5 to get boot configYe Li2021-08-091-1/+1
| | | | | | | | | | | | | | | | | | Since CMC1 MR0 only reflects high 16 bits boot cfg used for AP domian, it does not connect to low 16 bits for RTD. So we can't get the correct boot mode. Change to use DGO_GP5 of SEC_SIM which is set by ROM. Signed-off-by: Ye Li <ye.li@nxp.com>
| * imx8ulp: soc: correct reset causePeng Fan2021-08-091-7/+3
| | | | | | | | | | | | | | | | | | The CMC1 SRS reflects the current reset cause, not SSRS. Then you could get "Reset cause: WARM-WDG" when issue reset in U-Boot. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: add iomuxc supportPeng Fan2021-08-091-1/+55
| | | | | | | | | | | | Add i.MX8ULP iomuxc support Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: add dummy imx_get_mac_from_fusePeng Fan2021-08-091-0/+5
| | | | | | | | | | | | Add imx_get_mac_from_fuse for enet build pass Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domainYe Li2021-08-091-0/+2
| | | | | | | | | | | | | | Configure DCNANO and MIPI_DSI to be controlled by AD for single boot Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: iMX8ULP: Add boot device relevant functionsYe Li2021-08-091-0/+84
| | | | | | | | | | | | | | Read from ROM API to get current boot device. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: Probe the S400 MU device in arch initYe Li2021-08-091-1/+34
| | | | | | | | | | | | | | | | Need probe the S400 MU device in arch_cpu_init_dm, so we can use S400 API in u-boot Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx8ulp: unify rdc functionsPeng Fan2021-08-092-173/+290
| | | | | | | | | | | | | | Unify rdc function to rdc.c Update soc.c to use new rdc function Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: release trdc and assign lpav from RTD to APDPeng Fan2021-08-091-1/+103
| | | | | | | | | | | | | | | | | | | | | | | | Rlease LPAV from RTD to APD Release gpu2D/3D to APD Set TRDC MBC2 MEM1 for iomuxc0 access Since upower depends AP/M33 SW to configure IOMUX for its PMIC i2c and MODE pins. we have to open iomuxc0 access for A35 core (domain 7) in single boot. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
| * arm: imx8ulp: add trdc release requestPeng Fan2021-08-091-9/+17
| | | | | | | | | | | | | | Add TRDC release request, then we could configure resources to be accessible by A35 Domain. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: add rdc supportPeng Fan2021-08-092-1/+145
| | | | | | | | | | | | | | There is xrdc inside i.MX8ULP, we need to configure permission to make sure AP non-secure world could access the resources. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: release and configure XRDC at early phaseYe Li2021-08-092-8/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since S400 will set the memory of SPL image to R/X. We can't write to any data in SPL image. 1. Set the parameters save/restore only for u-boot, not for SPL. to avoid write data. 2. Not use MU DM driver but directly call MU API to send release XRDC to S400 at early phase. 3. Configure the SPL image memory of SRAM2 to writable (R/W/X) Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: Update the reset vector in u-bootYe Li2021-08-091-13/+22
| | | | | | | | | | | | | | | | Because we have set reset vector to ATF in SPL, have to set it back to ROM for any reset in u-boot Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: disable wdog3Peng Fan2021-08-091-1/+35
| | | | | | | | | | | | Disable wdog3 which is configured by ROM Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: Enable full L2 cache in SPLYe Li2021-08-091-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SRAM2 is half L2 cache and default to SRAM after system boot. To enable the full l2 cache (512KB), it needs to reset A35 to make the change happen. So re-implement the jump entry function in SPL: 1. configure the core0 reset vector to entry (ATF) 2. enable the L2 full cache 3. reset A35 So when core0 up, it runs into ATF. And we have 512KB L2 cache working. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: soc: Change to use CMC1 to get bootcfgYe Li2021-08-091-1/+1
| | | | | | | | | | | | CMC1 also has a MR register for bootcfg Signed-off-by: Ye Li <ye.li@nxp.com>
| * arm: imx8ulp: add clock supportPeng Fan2021-08-095-3/+1280
| | | | | | | | | | | | Add i.MX8ULP clock support Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx: move container Kconfig under mach-imxPeng Fan2021-08-092-13/+13
| | | | | | | | | | | | | | Since i.MX8 and i.MX8ULP reuse common container, so move the Kconfig public to both. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: add container supportYe Li2021-08-094-46/+172
| | | | | | | | | | | | | | | | | | i.MX8ULP support using ROM API to load container image, it use same ROM API as i.MX8MN/MP, and use same container format as i.MX8QM/QXP. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx: parse-container: guard included header filesPeng Fan2021-08-091-0/+2
| | | | | | | | | | | | | | Guard included sci.h with CONFIG_AHAB_BOOT to avoid build failure for i.MX8ULP Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8: Move container image header file to mach-imxYe Li2021-08-094-4/+4
| | | | | | | | | | | | | | | | Since the container is shared among i.MX platforms, move its header file to mach-imx Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8: Move container parser and image to mach-imx common folderYe Li2021-08-094-3/+4
| | | | | | | | | | | | | | Since we will re-use the container parser on imx8ulp, move the codes to mach-imx Signed-off-by: Ye Li <ye.li@nxp.com>
| * arm: imx: basic i.MX8ULP supportPeng Fan2021-08-096-2/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | Add basic i.MX8ULP support For the MMU part, Using a simple way the calculate the MMU size to avoid default heavy calcaulation. And align address and size in the table settings to 2MB or 4GB as much as possible. So we can reduce the 4K page allocations in MMU table which will spends much time in create the page table Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx8ulp: add get reset causePeng Fan2021-08-091-0/+69
| | | | | | | | | | | | Add get reset cause function to show what triggerred reset. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx8ulp: support print cpu infoPeng Fan2021-08-091-0/+58
| | | | | | | | | | | | | | Support print cpu info. the clock function has not been added, it will be added in following patches. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx: add i.MX8ULP cpu type and helperPeng Fan2021-08-091-0/+11
| | | | | | | | | | | | Add i.MX8ULP cpu type and helpers. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm: imx: add i.MX8ULP basic Kconfig optionPeng Fan2021-08-091-0/+16
| | | | | | | | | | | | Add i.MX8ULP related basic Kconfig option, which will be used later. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | pci: imx: Drop DM_PCI check from cpu driverSimon Glass2021-08-051-4/+0
|/ | | | | | | | | We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* global: Convert simple_strtoul() with decimal to dectoul()Simon Glass2021-08-023-3/+3
| | | | | | | It is a pain to have to specify the value 10 in each call. Add a new dectoul() function and update the code to use it. Signed-off-by: Simon Glass <sjg@chromium.org>
* global: Convert simple_strtoul() with hex to hextoul()Simon Glass2021-08-028-41/+41
| | | | | | | | | It is a pain to have to specify the value 16 in each call. Add a new hextoul() function and update the code to use it. Add a proper comment to simple_strtoul() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* Rename GPIO_SUPPORT to GPIOSimon Glass2021-07-281-1/+1
| | | | | | Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
* Rename SPL_USB_HOST_SUPPORT to SPL_USB_HOSTSimon Glass2021-07-281-1/+1
| | | | | | Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org>
* Rename SPL_WATCHDOG_SUPPORT to SPL_WATCHDOGSimon Glass2021-07-281-1/+1
| | | | | | Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org>
* usb: Enforce DM_USB migration for USB_HOST devices.Tom Rini2021-07-182-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | As the deadline for migration to DM_USB, when using a USB host controller has now gone two years past the deadline, enforce migration. This is done by: - Ensuring that all host controller options (other than the very legacy old MUSB ones) now select USB_HOST. USB_HOST now enforces DM_USB and OF_CONTROL. - Remove other parts of Kconfig logic that had platforms pick DM_USB. - To keep Kconfig happy, have some select statements test for USB_HOST as well. - Re-order some Kconfig entries and menus so that we can cleanly pick host or gadget roles. For the various HCD options that have platform glue options, group them together and update dependencies in some cases. - As SPL_DM_USB is not required, on platforms that had not yet enabled it, disable it. Cc: Marek Vasut <marex@denx.de> Cc: Icenowy Zheng <icenowy@aosc.io> Cc: Samuel Holland <samuel@sholland.org> Cc: FUKAUMI Naoki <naobsd@gmail.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: imx8mq: Add USB clock init functionYe Li2021-07-171-0/+22
| | | | | | | | | Add clock function to setup relevant clocks for USB3.0 controllers and PHYs on i.MX8MQ Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se>
* ARM: imx: Pick correct eMMC boot partition from ROM logMarek Vasut2021-07-101-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the iMX8M boot from eMMC boot partition and the primary image is corrupted, the BootROM is capable of starting a secondary image in the other eMMC boot partition as a fallback. However, the BootROM leaves the eMMC BOOT_PARTITION_ENABLE setting as it was, i.e. pointing to the boot partition containing the corrupted image, and the BootROM does not provide any indication that this sort of fallback occured. According to AN12853 i.MX ROMs Log Events, Rev. 0, May 2020, it is possible to determine whether fallback event occurred by parsing the ROM event log. In case ROM event ID 0x51 is present, fallback event did occur. This patch implements ROM event log parsing and search for event ID 0x51 for all iMX8M SoCs, and based on that corrects the eMMC boot partition selection. This way, the SPL loads the remaining boot components from the same eMMC boot partition from which it was started, even in case of the fallback. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Faiz Abbas <faiz_abbas@ti.com> Cc: Harald Seiler <hws@denx.de> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com>
* arm/mach-imx: Fix macros in mmdc_size.cKacper Kubkowski2021-07-101-5/+5
| | | | | | | | Make macros actually use passed parameter instead of local variables that happen to be named the same as symbols in macro expansion. Signed-off-by: Kacper Kubkowski <kkubkowski@fluence.pl>
* board: phytec: imx8mp-phycore: Switch to binmanTeresa Remmet2021-07-101-0/+1
| | | | | | | | Use now binman for image creation. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* imx8m: Restrict usable memory to space below 4G boundaryFrieder Schrempf2021-07-101-0/+14
| | | | | | | | | | | | Some IPs have their accessible address space restricted by the interconnect. Let's make sure U-Boot only ever uses the space below the 4G address boundary (which is 3GiB big), even when the effective available memory is bigger. We implement board_get_usable_ram_top() for all i.MX8M SoCs, as the whole family is affected by this. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
* mx7d: Add Storopack's SMEGW01 boardFabio Estevam2021-06-091-0/+9
| | | | | | | | | Add support for Storopack's SMEGW01 board, which is an IoT gateway based on the i.MX7D SoC. Based on the original U-Boot work done by Phytec. Signed-off-by: Fabio Estevam <festevam@denx.de>
* imx: Add SeeedStudio NPI-IMX6ULL SupportNavin Sankar Velliangiri2021-06-091-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU: Freescale i.MX6ULL rev1.1 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 49C Reset cause: POR Model: Seeed NPi iMX6ULL Dev Board with NAND Board: Seeed NPi i.MX6ULL Dev Board DRAM: 512 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: FEC0 Working: - Eth0 - MMC/SD - NAND - UART 1 - USB host Signed-off-by: Navin Sankar Velliangiri <navin@linumiz.com> Note: Changes in v2: * removed unnecessary space in imx6ull-seeed-npi-imx6ull-dev-board.dts file. * Used SZ_2M for CONFIG_SYS_MALLOC_LEN size allocation.
* imx: support for conga-QMX8 boardOliver Graute2021-06-091-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8QM qmx8 congatec board support U-Boot 2021.07-rc3-00528-gc9a966d9dd (May 31 2021 - 15:21:25 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Congatec QMX8 Qseven series Board: conga-QMX8 Build: SCFW 494c97f3, SECO-FW d63fdb21, ATF 09c5cc9 Boot: SD2 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 switch to partitions #0, OK mmc2 is current device Net: Error: ethernet@5b040000 address not set. No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
* arm: imx: imx8mm: correct unrecognized fracpll frequencyAndrey Zhizhikin2021-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ() macro, which expands the value provided to the Hz range without taking into account the precise Hz setting. This causes the frequency of 266 MHz not ot be found in the imx8mm_fracpll_tbl, since it is entered there with a precise Hz value. This in turn causes the boot hang in SPL, as proper DDR fracpll frequency cannot be determined. Correct the value in imx8mm_fracpll_tbl to match the one expanded by MHZ(266) macro, rounding it down to MHz range only. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m") Reviewed-by: Fabio Estevam <festevam@gmail.com>
* arm: imx: imx8mm: clock: make debug output more descriptiveAndrey Zhizhikin2021-06-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | Clock initialization functionality has ambitious debug messages, which are printed out when failures are triggered during execution: - Separate frequency table lookup functions have the the same output that makes it impossible to understand which function failed and produced the output - PLL decoding routine has a generic debug statement printed, which does not state the actual value failed to be found Extend the output for both cases with prefixing table lookup functions output with function name, and report the failed value in PLL decoding routine. Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
View Lorry Controller Status