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* mx7d: Add Storopack's SMEGW01 boardFabio Estevam2021-06-091-0/+9
| | | | | | | | | Add support for Storopack's SMEGW01 board, which is an IoT gateway based on the i.MX7D SoC. Based on the original U-Boot work done by Phytec. Signed-off-by: Fabio Estevam <festevam@denx.de>
* imx: Add support for Ronetix's iMX7-CM boardIlko Iliev2021-05-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Console boot log: U-Boot SPL 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200) Trying to boot from MMC1 U-Boot 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200) CPU: Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 44C Reset cause: POR Model: Ronetix iMX7-CM Board Board: iMX7-CM DRAM: 512 MiB PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11 MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 (eth0) using random MAC address - fe:be:37:01:5a:3f eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 Signed-off-by: Ilko Iliev <iliev@ronetix.at>
* common: Drop asm/global_data.h from common headerWIP/2021-02-02-drop-asm_global_data-when-unusedSimon Glass2021-02-021-0/+1
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextWIP/05Jan2021-nextTom Rini2021-01-051-1/+1
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * dm: Rename U_BOOT_DEVICE() to U_BOOT_DRVINFO()Simon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current macro is a misnomer since it does not declare a device directly. Instead, it declares driver_info record which U-Boot uses at runtime to create a device. The distinction seems somewhat minor most of the time, but is becomes quite confusing when we actually want to declare a device, with of-platdata. We are left trying to distinguish between a device which isn't actually device, and a device that is (perhaps an 'instance'?) It seems better to rename this macro to describe what it actually is. The macros is not widely used, since boards should use devicetree to declare devices. Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is declaring a new driver_info record, not a device. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-051-11/+11
|\ \ | |/ |/| | | | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * imx: mx7: clock: use correct format stringsHeinrich Schuchardt2020-12-261-11/+11
| | | | | | | | | | | | | | | | Use %u and not %d for unsigned values. Print kHz and not khz. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-131-1/+1
|/ | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: imx: ddr: Add deskew register programmingMarek Vasut2020-08-171-0/+9
| | | | | | | | | | | Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers, which are optional, but can be used to fill in the byte lane delays. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: Add support for reading out the primary/secondary bmode to MX7Marek Vasut2020-08-171-0/+7
| | | | | | | | | | | | | | Implement the 'getprisec' subcommand of 'bmode' command for i.MX7 by reading out the SRC GPR10 bit 30. This bit is either set by the BootROM if it switched to the secondary copy due to primary copy being corrupted OR it can be overridden by the user. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* ARM: imx: Add support for switching primary/secondary boot mode to bmodeMarek Vasut2020-08-171-0/+2
| | | | | | | | | | | | | | | The i.MX6/i.MX7 is capable of booting a secondary "redundant" system image in case the primary one is corrupted. The user can force this boot mode as well by explicitly setting SRC GPR10 bit 30. This can be potentially useful when upgrading the bootloader itself. Expose this functionality to the user. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* ARM: imx: Add bmode support for iMX7Marek Vasut2020-08-171-0/+8
| | | | | | | | | | | Add the basic differentiation between i.MX6 and i.MX7 into the bmode command, the mechanism really works almost the same on both platforms. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx7: fix DDRC size in A7-M4 mapping tableIgor Opaniuk2020-07-271-1/+1
| | | | | | | | | | According to i.MX 7Solo Applications Processor Reference Manual, 2.1.3 Cortex-M4 Memory Map, M4 can address only 1536MB of DDRC (Start Address: 0x8000_0000; End Address: 0xDFFF_FFFF). Correct DDRC size to 0x60000000. Fixes: c0f037f6("mach-imx: bootaux: elf firmware support") Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
* ARM: imx: soc: Select default TEXT_BASE for MX7Marek Vasut2020-06-221-0/+7
| | | | | | | | | | | | | | | | | | | | | Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot text base is picked as the one used by various MX7 boards. The SPL text base however is different. The SPL text base is set to 0x912000 instead of the usual 0x911000, that is because the 0x911000 value cannot work. Using 0x911000 as a SPL text base will result in the DCD header being placed below the 0x911000 address, which is a reserved SRAM area which must not be used. This will actually trigger eMMC boot failure on MX7D at least. Hence the increment. Update all boards affected by this SPL problem to the new SPL_TEXT_BASE. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7Marek Vasut2020-06-221-0/+1
| | | | | | | | | | | | | | | | The iMX7 defines further DDRC ZQCTLx registers, however those were thus far missing from the list of registers and not programmed. On systems with LPDDR2 or DDR3, those registers must be programmed with correct values, otherwise the DRAM may not work. However, existing systems which worked without programming these registers before are now setting those registers to 0, which is the default value, so no functional change there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: ddr: Add missing PHY resetMarek Vasut2020-06-081-3/+19
| | | | | | | | | | | | | | | | | The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power explicitly says both the DDR controller and the PHY must be reset in the correct sequence. Currently the code only resets the controller. This leads to a misbehavior where the system brings the DRAM up after reboot, but the DRAM is unstable. Add the missing reset. The easiest way to trigger this is by triggering WDT without having the WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* command: Remove the cmd_tbl_t typedefSimon Glass2020-05-181-1/+3
| | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop net.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move clock functions into a new fileSimon Glass2020-01-171-0/+1
| | | | | | | These three clock functions don't use driver model and should be migrated. In the meantime, create a new file to hold them. Signed-off-by: Simon Glass <sjg@chromium.org>
* mach-imx: bootaux: elf firmware supportIgor Opaniuk2020-01-071-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently imx-specific bootaux command doesn't support ELF format firmware for Cortex-M4 core. This patches introduces a PoC implementation of handling elf firmware (load_elf_image_phdr() was copy-pasted from elf.c just for PoC). ELF64 binaries isn't supported yet. This has the advantage that the user does not need to know to which address the binary has been linked to. However, in order to handle and load the elf sections to the right address, we need to translate the Cortex-M4 core memory addresses to primary/host CPU memory addresses (Cortex A7/A9 cores). This allows to boot firmwares from any location with just using bootaux, e.g.: > tftp ${loadaddr} hello_world.elf && bootaux ${loadaddr} Similar translation table can be found in the Linux remoteproc driver [1]. [1] https://elixir.bootlin.com/linux/latest/source/drivers/remoteproc/imx_rproc.c Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
* common: Move ARM cache operations out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | | | These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Add i.MX7D based Meerkat96 board supportShawn Guo2019-10-131-0/+10
| | | | | | | | | | | | | | | | | | | | | The Meerkat96 board, based on the NXP i.MX7D SoC, is a member of 96Boards community and complies with all Consumer Edition board specifications. https://www.novtech.com/products/meerkat96.html https://www.96boards.org/product/imx7-96/ The initial supported/tested devices include: - Debug serial - SD - USB Host (with Ethernet) With these support, it's good enough for loading Linux Kernel from SD or Ethernet over USB. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HABStefano Babic2019-10-082-2/+2
| | | | | | | | CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic <sbabic@denx.de>
* env: Move env_set() to env.hSimon Glass2019-08-111-0/+1
| | | | | | | Move env_set() over to the new header file. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* psci: Fix warnings when compiling with W=1Patrick Delaunay2019-07-241-1/+1
| | | | | | | | | | | | | | | | | | This patch solves the following warnings: arch/arm/mach-stm32mp/psci.c: warning: no previous prototype for ‘psci_set_state’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_arch_cpu_entry’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_features’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_version’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_affinity_info’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_migrate_info_type’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_on’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_cpu_off’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_reset’ [-Wmissing-prototypes] warning: no previous prototype for ‘psci_system_off’ [-Wmissing-prototypes] Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* Convert to use fsl_esdhc_imx for i.MX platformsYangbo Lu2019-06-231-2/+2
| | | | | | | | | | | Converted to use fsl_esdhc_imx for i.MX platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
* Merge tag 'u-boot-imx-20190612' of git://git.denx.de/u-boot-imxTom Rini2019-06-112-16/+29
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot-imx-20190612 -------------------- - Board fixes: - imx6logic - wandboard - mx6sabre boots again - imx8qm_mek - pico-* boards - Toradex apalis / colibri - engicam imx6 (environment) - KP MX53 - opos6ul - Switch to DM: - vining2000 - dh MX6 - Toradex colibri i.MX7 - Novena - Security : fix CSF size for HAB - Other: - imx: fix building for i.mx8 without spl - pcie and switch to DM mx6sabreauto: Enable SPL SDP support
| * pico-imx7d: Correct uart clock rootJun Nie2019-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | Correct uart clock root ID. Incorrect ID may result the clock is gated because rate value 0 is returned in imx_get_uartclk() The ID can be ignored if CONFIG_SKIP_LOWLEVEL_INIT is not enabled because init_clk_uart() will enable all uart clocks in that case. Signed-off-by: Jun Nie <jun.nie@linaro.org>
| * imx: mx7: Skip secure init in arch_cpu_initJun Nie2019-06-111-15/+28
| | | | | | | | | | | | | | | | Skip secure related initialization in arch_cpu_init if low level init is skipped. Because these should be done in early stage firmware, such as ARM trusted firmware. Signed-off-by: Jun Nie <jun.nie@linaro.org>
* | video: mxsfb: add DM_VIDEO supportIgor Opaniuk2019-06-041-1/+1
|/ | | | | | | | Extend the driver to build with DM_VIDEO enabled. DTS files must additionally include 'u-boot,dm-pre-reloc' property in soc and child nodes to enable driver binding to mxsfb device. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
* mx7: Do not call lcdif_power_down() in the SPL caseFabio Estevam2019-01-281-0/+2
| | | | | | | | | | | | | | | | | | | | Like it was done on imx6 in commit 9236269de57d ("imx: mx6: Fix implementantion reset_misc") Do not call lcdif_power_down() in the SPL case to fix the following build error: LD spl/u-boot-spl MKIMAGE u-boot.img arch/arm/mach-imx/built-in.o: In function `reset_misc': /home/fabio/ossystems/u-boot/arch/arm/mach-imx/mx7/soc.c:372: undefined reference to `lcdif_power_down' scripts/Makefile.spl:375: recipe for target 'spl/u-boot-spl' failed Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx: mx7: avoid some initialization if low level is skippedRui Miguel Silva2018-10-221-0/+2
| | | | | | | | | | | | | | | | | | | We can have the case where u-boot is launched after some other low level enabler, like for example when u-boot runs after arm-trusted-firmware and/or optee. So, because of that we may need to jump the initialization of some IP blocks even because we may no longer have the permission for that. So, if the config option to skip low level init is set disable also timer, board and csu initialization. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Peng Fan <peng.fan@nxp.com> Cc: u-boot@lists.denx.de Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx: mx7: fix potential overflow in imx_ddr_size()Marcel Ziswiler2018-10-091-0/+4
| | | | | | | | | The imx_ddr_size() function may overflow as it is possible to kind of over provision the DDR controller. Fix this by capping it to 2 GB which is the maximum allowed size as per reference manual. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
* imx: mx7: add system suspend/resume supportAnson Huang2018-09-043-3/+515
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds system suspend/resume support, when linux kernel enters deep sleep mode, SoC will go into below mode: - CA7 platform goes into STOP mode; - SoC goes into DSM mode; - DDR goes into self-refresh mode; - CPU0/SCU will be powered down. When wake up event arrives: - SoC DSM mdoe exits; - CA7 platform exit STOP mode, SCU/CPU0 power up; - Invalidate L1 cache; - DDR exit self-refresh mode; - Do secure monitor mode related initialization; - Jump to linux kernel resume entry. Belwo is the log of 1 iteration of system suspend/resume: [ 338.824862] PM: suspend entry (deep) [ 338.828853] PM: Syncing filesystems ... done. [ 338.834433] Freezing user space processes ... (elapsed 0.001 seconds) done. [ 338.842939] OOM killer disabled. [ 338.846182] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. [ 338.869717] PM: suspend devices took 0.010 seconds [ 338.877846] Disabling non-boot CPUs ... [ 338.960301] Retrying again to check for CPU kill [ 338.964953] CPU1 killed. [ 338.968104] Enabling non-boot CPUs ... [ 338.973598] CPU1 is up [ 339.267155] mmc1: queuing unknown CIS tuple 0x80 (2 bytes) [ 339.275833] mmc1: queuing unknown CIS tuple 0x80 (7 bytes) [ 339.284158] mmc1: queuing unknown CIS tuple 0x80 (6 bytes) [ 339.385065] PM: resume devices took 0.400 seconds [ 339.389836] OOM killer enabled. [ 339.392986] Restarting tasks ... done. [ 339.398990] PM: suspend exit The resume entry function has to initialize stack pointer before calling C code, otherwise there will be an external abort occur, in additional, invalidate L1 cache must be done in secure section as well, so this patch also adds assembly code back and keep it as simple as possible. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Tested-by: Stefan Agner <stefan@agner.ch>
* imx: mx7: add gpc initialization for low power modeAnson Huang2018-09-041-0/+103
| | | | | | | | | | | | | | | Add i.MX7D GPC initialization for low power mode support like system suspend/resume from linux kernel: - Pending IOMUXC IRQ to workaround GPC state machine issue; - Mask all GPC interrupts for M4/C0/C1; - Configure SCU timing; - Configure time slot ack; - Configure C0/C1 power up/down timing; - Configure wakeup source mechanism; - Disable DSM/RBC related settings. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* imx: mx7: psci: improve cpu hotplug flowAnson Huang2018-09-041-2/+21
| | | | | | | | | | | | | | | | This patch improves cpu hotplug, previous cpu_off implementation is NOT safe, a CPU can NOT power down itself in runtime, it will cause system bus hang due to pending transaction. So need to use other online CPU to kill it when it is ready for killed. Here use SRC parameter register and a magic number of ~0 as handshake for killing a offline CPU, when the online CPU checks the psci_affinity_info, it will help kill the offline CPU according to the magic number stored in SRC parameter register. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
* dm: Fix CMD_DM enablingMichal Simek2018-07-311-1/+1
| | | | | | | | | | The patch "dm: Change CMD_DM enabling" (sha1: 08a00cba06a7e608ae65e3d7ea225cf8c639429d) was incorrectly updated and PICO_IMX7D is missing imply CMD_DM and WARP7 has it twice. This patch is fixing it. Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: Change CMD_DM enablingMichal Simek2018-07-301-0/+5
| | | | | | | | | | | CMD_DM is used for debug purpose and it shouldn't be enabled by default via Kconfig. Unfortunately this is in the tree for quite a long time that's why solution is to use imply DM for all targets which are enabling DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* Kconfig: Sort bool, default, select and imply optionsMichal Simek2018-07-301-9/+9
| | | | | | | | Fix Kconfig bool, default, select and imply options to be alphabetically sorted. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* pico-imx7d: Add SPL supportFabio Estevam2018-07-231-0/+1
| | | | | | | | | | | | | | | | | | | Convert pico-imx7d to SPL support. There are two variants of pico-imx7d SOMs: - One with 512MB of RAM - One with 1GB of RAM The 512MB module contains two Hynix H5TC2G63GFR-PBA. The 1GB module contains two Hynix H5TC4G63GFR-PBA. The RAM size is determined in runtime by reading GPIO1_12. While at it, also add USB Serial Download mode support as it is very helpful for loading SPL and u-boot.img via imx_usb_loader. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* imx: mx7: psci: implement MIGRATE_INFO_TYPEStefan Agner2018-07-231-0/+7
| | | | | | | | Implement MIGRATE_INFO_TYPE. This informs Linux that no migration for the trusted operating system is necessary: [ 0.000000] psci: Trusted OS migration not required Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* imx: mx7: psci: support CPU0 on/offStefan Agner2018-07-231-8/+12
| | | | | | | | | | | | | | | | | | | | | | | So far psci_cpu_(on|off) only worked for CPU1. Allow to control CPU0 too. This allows to run the Linux PSCI checker successfully: [ 2.213447] psci_checker: PSCI checker started using 2 CPUs [ 2.219107] psci_checker: Starting hotplug tests [ 2.223859] psci_checker: Trying to turn off and on again all CPUs [ 2.267191] IRQ21 no longer affine to CPU0 [ 2.293266] Retrying again to check for CPU kill [ 2.302269] CPU0 killed. [ 2.311648] psci_checker: Trying to turn off and on again group 0 (CPUs 0-1) [ 2.354354] IRQ21 no longer affine to CPU0 [ 2.383222] Retrying again to check for CPU kill [ 2.392148] CPU0 killed. [ 2.398063] psci_checker: Hotplug tests passed OK [ 2.402910] psci_checker: Starting suspend tests (10 cycles per state) [ 2.410019] psci_checker: cpuidle not available on CPU 0, ignoring [ 2.416452] psci_checker: cpuidle not available on CPU 1, ignoring [ 2.422757] psci_checker: Could not start suspend tests on any CPU [ 2.429370] psci_checker: PSCI checker completed Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* imx: mx7: psci: provide complete PSCI 1.0 implementationStefan Agner2018-07-231-3/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PSCI 1.0 require PSCI_VERSION, PSCI_FEATURES, AFFINITY_INFO and CPU_SUSPEND to be implemented. Commit 0ec3d98f7692 ("mx7_common: use psci 1.0 instead of 0.1") marked the i.MX 7 implementation to be PSCI 1.0 compliant but failed to implement those functions. Especially the missing PSCI version callback was noticeable when booting Linux: [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv65535.65535 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.0 This patch provides a minimal implementation thereof. With this patch applied Linux detects PSCI 1.0: [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.0 Fixes: 0ec3d98f7692 ("mx7_common: use psci 1.0 instead of 0.1") Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* imx: mx7: psci: use C code exclusivelyStefan Agner2018-07-233-70/+24
| | | | | | | | | | There is no need for assembly in the platform specific part of the PSCI implementation. Note that this does not make it a complete PSCI 1.0 implementation yet but aids to do so in upcoming patches. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* mx7: Remove BMODE supportFabio Estevam2018-07-232-26/+0
| | | | | | | | i.MX7 does not support BMODE due to the erratum e10574 ("Watchdog: A watchdog timeout or software trigger will not reset the SOC"), so remove its support. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platformsYe Li2018-06-181-7/+0
| | | | | | | | | | | | | | According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com> [fabio: adapted to U-Boot mainline codebase and make checkpatch happy] Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
* imx7: psci: save context id in cpu_on commandPatrick Delaunay2018-05-071-1/+2
| | | | | | | Replace the psci_save_target_pc call by the new function psci_save(cpu, pc,context_id) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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