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* ARM: imx: Pick correct eMMC boot partition from ROM logMarek Vasut2021-07-101-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the iMX8M boot from eMMC boot partition and the primary image is corrupted, the BootROM is capable of starting a secondary image in the other eMMC boot partition as a fallback. However, the BootROM leaves the eMMC BOOT_PARTITION_ENABLE setting as it was, i.e. pointing to the boot partition containing the corrupted image, and the BootROM does not provide any indication that this sort of fallback occured. According to AN12853 i.MX ROMs Log Events, Rev. 0, May 2020, it is possible to determine whether fallback event occurred by parsing the ROM event log. In case ROM event ID 0x51 is present, fallback event did occur. This patch implements ROM event log parsing and search for event ID 0x51 for all iMX8M SoCs, and based on that corrects the eMMC boot partition selection. This way, the SPL loads the remaining boot components from the same eMMC boot partition from which it was started, even in case of the fallback. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Faiz Abbas <faiz_abbas@ti.com> Cc: Harald Seiler <hws@denx.de> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com>
* imx8m: Restrict usable memory to space below 4G boundaryFrieder Schrempf2021-07-101-0/+14
| | | | | | | | | | | | Some IPs have their accessible address space restricted by the interconnect. Let's make sure U-Boot only ever uses the space below the 4G address boundary (which is 3GiB big), even when the effective available memory is bigger. We implement board_get_usable_ram_top() for all i.MX8M SoCs, as the whole family is affected by this. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
* ARM: make gd a function call for LTO and set via set_gd()Marek Behún2021-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM, the gd pointer is stored in registers r9 / x18. For this the -ffixed-r9 / -ffixed-x18 flag is used when compiling, but using global register variables causes errors when building with LTO, and these errors are very difficult to overcome. Richard Biener says [1]: Note that global register vars shouldn't be used with LTO and if they are restricted to just a few compilation units the recommended fix is to build those CUs without -flto. We cannot do this for U-Boot since all CUs use -ffixed-reg flag. It seems that with LTO we could in fact store the gd pointer differently and gain performance or size benefit by allowing the compiler to use r9 / x18. But this would need more work. So for now, when building with LTO, go the clang way, and instead of declaring gd a global register variable, we make it a function call via macro. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68384 Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: imx: Add OCRAM_S into iMX8M MMU tablesMarek Vasut2021-04-081-0/+7
| | | | | | | | | | The OCRAM_S is regular memory, just like the OCRAM, add it to the MMU tables so it can be used and cached. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* iMX8MQ: Recognize the B2 revisionYe Li2021-04-081-1/+10
| | | | | | | | | | | | i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so we have to check the ROM verision to distinguish the revision. As we have checked the B1 rev for sticky bits work around in secure boot. So it won't apply on B2. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: soc: update fuse pathPeng Fan2021-04-081-5/+10
| | | | | | | Update fuse path to disable modules correctly. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: Update thermal and PMU kernel nodes for dual/single coresYe Li2021-04-081-0/+76
| | | | | | | | | | For dual core and single core iMX8M parts, the thermal node and PMU node in kernel DTB also needs update to remove the refers to deleted core nodes. Otherwise both driver will fail to work. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn: Add support for 11x11 UltraLite part numberYe Li2021-04-081-12/+24
| | | | | | | | | | | | There are 3 part numbers for 11x11 i.MX8MNano with different core number configuration: UltraLite Quad/Dual/Solo Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So checking the MIPI DSI disable fuse to recognize these parts. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn: Add low drive mode support for DDR4/LPDDR4 EVKYe Li2021-04-081-0/+45
| | | | | | | | | Add dedicated defconfigs for iMX8MN low drive mode which set the VDD_SOC and VDD_DRAM to 0.8v, DDR at 1600MTS (800Mhz clock) and GPU at 200Mhz. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Merge tag 'v2021.04-rc4' into nextTom Rini2021-03-151-3/+16
|\ | | | | | | Prepare v2021.04-rc4
| * ARM: imx: Do not hard-code MX8M MMU table DRAM entry offsetMarek Vasut2021-03-011-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of hard-coding the offset of DRAM entries in MMU table all over the code, auto-detect the offset. This removes error-prone code which would break e.g. in case the MMU table is modified. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* | reset: Remove addr parameter from reset_cpu()Harald Seiler2021-03-021-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/global_data.h from common headerWIP/2021-02-02-drop-asm_global_data-when-unusedSimon Glass2021-02-021-0/+1
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* imx8m: fix cache setup for dynamic sdram sizeTim Harvey2020-12-061-0/+3
| | | | | | | | | | | the mem_map structure containing the size of SDRAM is used in various cache functions in cache_v8.c thus we need to update it with the sdram size the board is configured with as well. Without this the cache functions do not get setup properly and can hang in the case where a board reports more SDRAM than defined in PHYS_SDRAM_SIZE. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 supportPeng Fan2020-09-171-8/+4
| | | | | | | | Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so update u-boot to remove decoding and support for those parts. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: soc: Remove unneeded spaceFabio Estevam2020-07-271-1/+1
| | | | | | | | | | | | | | | Checkpatch reports the following issue: ERROR: space prohibited before that ',' (ctx:WxW) #936: FILE: arch/arm/mach-imx/imx8m/soc.c:936: + 0, 0 , 0, 0, 0, 0, &res); Remove the unneeded space. ^ Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada2020-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
* imx8m: Refactor the OPTEE memory removalPeng Fan2020-07-141-7/+115
| | | | | | | | | | | | | | | Current codes assume the OPTEE address is at the end of first DRAM bank. Adjust the process to allow OPTEE in the middle of first bank. When OPTEE memory is removed from first bank, it may split the first bank to two banks, adjust the MMU table for the split case, Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge i.MX8MP evk to default to avoid issue. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Tested-by: Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: disable nodes before kernel/mfgtool boot for fused partPeng Fan2020-07-141-0/+333
| | | | | | | | | To fused part, we need to disable nodes of dtb to let kernel boot. To mfgtool, USB issue when using super-speed for mfgtool, temporally work around the problem to use high-speed only. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn/imx8mp: override env_get_offset and env_get_locationYe Li2020-07-141-0/+59
| | | | | | | | | | To use one defconfig for all boot device, we have to runtime set env offset and return env medium according to the boot device. This patch overrides the env_get_offset and env_get_location to implement the feature. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: power down fused coresPeng Fan2020-07-141-0/+19
| | | | | | | For non-Quad SoCs, the fused cpu cores could be powered down in SPL to save power. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: Add fused parts supportYe Li2020-07-141-1/+33
| | | | | | | | | | | | | | | | | | | iMX8MP has 6 fused parts in each qualification tier, with core, VPU, ISP, NPU or DSP fused respectively. The configuration tables for enabled modules: MIMX8ML8DVNLZAA Quad Core, VPU, NPU, ISP, DSP MIMX8ML7DVNLZAA Quad Core, NPU, ISP MIMX8ML6DVNLZAA Quad Core, VPU, ISP MIMX8ML5DVNLZAA Quad Core, VPU MIMX8ML4DVNLZAA Quad Lite MIMX8ML3DVNLZAA Dual Core, VPU, NPU, ISP, DSP Add the support in U-Boot Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: workaround ROM serrorPeng Fan2020-07-141-0/+38
| | | | | | | | | | | | | | | | | | | ROM SError happens on two cases: 1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but when ROM patch lock is fused, this write will cause SError. 2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB is field return mode, but the last 4K of ROM is still protected and cause SError. Since ROM mask SError until ATF unmask it, so then ATF always meets the exception. This patch works around the issue in SPL by enabling SPL Exception vectors table and the SError exception, take the exception to eret immediately to clear the SError. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: soc: use arm_smccc_smcPeng Fan2020-07-141-2/+5
| | | | | | Use arm_smccc_smc to replace call_imx_sip Signed-off-by: Peng Fan <peng.fan@nxp.com>
* common: Drop linux/bitops.h from common headerWIP/2020-05-18-reduce-size-of-common.hSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* imx8mp: Set default SNSR25C for TMU probe1Ye Li2020-05-101-0/+2
| | | | | | | | | | So far u-boot only load SNSR25C for TMU main probe (probe 0). However, kernel enables two probes. So it also needs to set default SNSR25C of TCALIV1 for blank samples. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: load calibration parameters from fuse for i.MX8MPYe Li2020-05-101-0/+45
| | | | | | | | | | i.MX8MP thermal which has two probes and supports temperature range from -40 to 125. The driver still uses default 1p HW calibration at 25C and loads calibration parameters from fuse. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: i.MX8MN: Enable loading TASR and TCALIV from fuseYe Li2020-05-101-1/+1
| | | | | | | | | | Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers value from fuse before enabling TMU calibration. Otherwise the calibration is not exact. Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mm: Load fuse for TMU TCALIV and TASRYe Li2020-05-101-1/+27
| | | | | | | | | | On iMX8MM, the default value of TMU registers TCALIV and TASR need be loaded from fuse. HW won't do this, it expect SW loads them before using TMU. Reviewed-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ARM: imx8m: Don't use the addr parameter of reset_cpu()Claudius Heine2020-05-011-4/+1
| | | | | | | | | | | | imx8m has the only implementation of reset_cpu() which does not ignore the addr parameter and instead gives it some meaning as the base address of watchdog registers. This breaks convention with the rest of U-Boot where the parameter is ignored and callers are passing in 0. Fixes: d2041725e84b ("imx8m: restrict reset_cpu") Co-developed-by: Harald Seiler <hws@denx.de> Signed-off-by: Harald Seiler <hws@denx.de> Signed-off-by: Claudius Heine <ch@denx.de>
* ARM: imx8m: Fix indentation of reset_cpu() functionHarald Seiler2020-05-011-2/+5
| | | | | | Use proper code-style, tabs instead of spaces for indentation. Signed-off-by: Harald Seiler <hws@denx.de>
* ARM: imx8m: Do not define do_reset() if sysreset is enabledMarek Vasut2020-05-011-1/+1
| | | | | | | | | | | | | | | The SPL can also be compiled with sysreset drivers just fine, so update the condition to cater for that option. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Flavio Suligoi <f.suligoi@asem.it> Cc: Harald Seiler <hws@denx.de> Cc: Igor Opaniuk <igor.opaniuk@toradex.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* ARM: imx: imx8m: Do not warn about cpu-idle-states if missingMarek Vasut2020-05-011-2/+4
| | | | | | | | | | | | | | | | | If the cpu-idle-states is missing from the DT in the first place, do not fail on removing in. Just move on and do not even print an error, since not being able to remove something which is not there in the first place is not an error and surely does not justify failing to boot. Turn the surrounding prints into debugs to reduce the useless noise. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* imx: imx8m: Don't use the addr parameter of reset_cpuClaudius Heine2020-05-011-4/+1
| | | | | | | | | | | | | imx8m has the only implementation of `reset_cpu` which does not ignore the addr parameter and instead gives it some meaning as the base address of watchdog registers. This breaks convention with the rest of U-Boot where the parameter is ignored and callers are passing in 0. Fixes: d2041725e84b ("imx8m: restrict reset_cpu") Co-Authored-by: Harald Seiler <hws@denx.de> Signed-off-by: Claudius Heine <ch@denx.de> Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
* imx8m: Enable WDOG_B for timeoutYe Li2020-05-011-10/+10
| | | | | | | | | | | | | | | When doing reset_cpu, in normal case the WDOG_B outputs immediately after we clean WDA bit. But on mscale, the WDOG_B may be later than internal reset, and cause PMIC not reset. As we enabled the SD3.0 support, the PMIC must be reset to reset SD card. Change the reset_cpu to enable the WDOG_B for timeout as well, and set WDOG timeout to 1s. Reviewed-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: acquire ATF commit hashPeng Fan2020-05-011-0/+24
| | | | | | | | Acquire ATF commit hash when booting U-Boot to make user easy to know the ATF version. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8m: add i.MX8MN variants supportPeng Fan2020-05-011-1/+18
| | | | | | | Add i.MX8MN variants support Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: imx8m: add i.MX8MQ Dual and QuadLite supportPeng Fan2020-05-011-1/+9
| | | | | | | Add i.MX8MQ Dual and QuadLite variants. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mp: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan2020-01-081-1/+1
| | | | | | | Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: get cpu id/type of i.MX8MPPeng Fan2020-01-081-2/+5
| | | | | | Support get i.MX8MP cpu id and cpu type Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: fix rom version check to unbreak some B0 chipsPatrick Wildt2019-12-091-0/+1
| | | | | | | | | | | | | | Recently the version check was improved to be able to determine that we're running on SoC revision 2.1. A check for B0 was tightened so that it now must equal 0x20 instead of being bigger than 0x20. On some B0 chips the value returned is 0x1020 instead of 0x20. This means even though it's B0, the check will fail and code relying on the correct chip revision will make wrong decisions. There is no documentation of those bits, but it seems that NXP always uses a byte to encode the revision. Thus remove the upper bits to fix the regression. Signed-off-by: Patrick Wildt <patrick@blueri.se>
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | | | | | | These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* imx: imx8m: fix boot when CONFIG_$(SPL_)CLK not definedPeng Fan2019-11-051-6/+8
| | | | | | | | | | When CONFIG_$(SPL_)CLK not defined, the clock controller device not exist, so to avoid boot failure for platform not have CONFIG_$(SPL_)CLK, add a check. Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn: add get_boot_devicePeng Fan2019-11-051-0/+48
| | | | | | | No ROM INFO structure on iMX8MN, use new ROM API to get boot device from ROM. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn: set BYPASS ID SWAP to avoid AXI bus errorsPeng Fan2019-11-051-1/+1
| | | | | | | Set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mn: support get_cpu_revPeng Fan2019-11-051-1/+3
| | | | | | Add a dummy cpu type and support get_cpu_rev for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8m: imx8mq: get chip rev for B1 revisionPeng Fan2019-11-031-7/+14
| | | | | | | | The i.MX8MQ B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id. It returns a magic number 0xff0055aa. update get_cpu_rev to support it, and enable ocotp clock to access ocotp. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HABStefano Babic2019-10-081-1/+1
| | | | | | | | CONFIG_SECURE_BOOT is too generic and forbids to use it for cross architecture purposes. If Secure Boot is required for imx, this means to enable and use the HAB processor in the soc. Signed-off-by: Stefano Babic <sbabic@denx.de>
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