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* Merge tag 'u-boot-rockchip-20201031' of ↵WIP/30Oct2020Tom Rini2020-10-3010-11/+344
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
| * rockchip: Add Engicam PX30.Core C.TOUCH 2.0Jagan Teki2020-10-302-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0Jagan Teki2020-10-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: Add Engicam PX30.Core EDIMM2.2 Starter KitJagan Teki2020-10-302-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * arm64: dts: rockchip: Add Engicam PX30.Core SOMMichael Trimarchi2020-10-301-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. General features: - Rockchip PX30 - Up to 2GB DDR4 - eMMC 4 GB expandible - rest of PX30 features PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards. Possible baseboards are, - EDIMM2.2 - C.TOUCH 2.0 Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter KitJagan Teki2020-10-302-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out SOM's like PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm64: dts: rockchip: Add chosen node for ROCK-Pi N8Jagan Teki2020-10-301-0/+6
| | | | | | | | | | | | | | | | | | Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board. This will help to get serial out messages. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: dts: tinker: remove unnecessary nodeStefan Agner2020-10-301-4/+0
| | | | | | | | | | | | | | | | The property reg-shift with the same value is present in the base device tree already. Remove unnecessary node from rk3288-tinker.dts. Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: dts: tinker: move i2c node to shared device treeStefan Agner2020-10-302-7/+7
| | | | | | | | | | | | | | | | | | The I2C EEPROM is present on Tinker Board S as well. Move the i2c node to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree. Cc: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellWIP/29Oct2020Tom Rini2020-10-292-6/+25
|\ \ | | | | | | | | | | | | | | | | | | - Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch) - Armada 8k: Use ATF serdes init instead of the "old" U-Boot version (Baruch) - Minor update to Octeon TX/TX2 defconfig (Stefan)
| * | arm: dts: armada-cp110-master: update nand-controllerBaruch Siach2020-10-291-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align node properties to kernel dts node. The change of compatible property does not affect any currently supported board. Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility with the current driver. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | arm: dts: armada-cp110-slave: add missing cps_nandShmuel Hazan2020-10-291-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align node properties to kernel dts node. Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility with the current driver. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* | | Merge tag 'xilinx-for-v2021.01-v2' of ↵Tom Rini2020-10-297-115/+150
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x
| * | | arm64: zynqmp: Fix zynqmp mini qspi max frequencyT Karthik Reddy2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For zynqmp qspi, frequencies up to 40MHz will work irrespective of feedback clock enabled or disabled. If we want higher than 40Mhz the feedback clock should be enabled. With spi-max-frequency 108MHz it is not working when the feedback clock is disabled. Change it to 40MHz so that it works irrespective of feedback clock enabled or disabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm64: versal: Update mini u-boot eMMC node parametersAshok Reddy Soma2020-10-272-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mini u-boot eMMC dt parameters are not in sync with full u-boot dt. Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write commands are failing. Increase frequency to 200Mhz to fix this issue. Add bus-width = <8>, non-removable and disable-wp properties to the node as this is eMMC. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Add Z-turn board V5Alexandre GRIVEAUX2020-10-274-108/+137
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding Z-turn board V5 to resolve the change between: "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035 "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031 At this time the S25FL128SAGNFI003 doesn't work because of bug: *** Warning - spi_flash_probe_bus_cs() failed, using default environment zynq-zturn was checked on V5 board, same error. Maybe Z-turn board have the same problem (board with W25Q128BVFIG). Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-10-297-0/+394
|\ \ \ | |/ / |/| | | | | | | | | | | - Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support
| * | board: kontron: add sl28 supportMichael Walle2020-10-237-0/+394
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for the Kontron SMARC-sAL28 board. This includes just the bare minimum to be able to bring up the board and boot linux. For now, the Single and Dual PHY variant is supported. Other variants will fall back to the basic variant. In particular, there is no watchdog support for now. This means that you have to disable the default watchdog, otherwise you'll end up in the recovery bootloader. See the board README for details. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiWIP/22Oct2020Tom Rini2020-10-221-10/+33
|\ \ \ | |/ / |/| | | | | | | | - sun8i emac changes (Andre) - SCP firmware (Samuel)
| * | sunxi: binman: Add support for including SCP firmwareSamuel Holland2020-10-221-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a System Control Processor, or SCP. ARM Trusted Firmware (ATF) communicates with the SCP over SCPI to implement the PSCI system suspend, shutdown and reset functionality. Currently, SCP firmware is optional; the system will boot and run without it, but system suspend will be unavailable. Since all communication with the SCP is mediated by ATF, the only thing U-Boot needs to do is load the firmware into SRAM. The SCP firmware occupies the last 16KiB of SRAM A2, immediately following ATF. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Update FIT component descriptionsSamuel Holland2020-10-221-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit d879616e9e64 ("spl: fit: simplify logic for FDT loading for non-OS boots"), the SPL looks at the "os" properties of FIT images to determine where to append the FDT. The "os" property of the "firmware" image also determines how to execute the next stage of the boot process, as in 1d3790905d9c ("spl: atf: introduce spl_invoke_atf and make bl31_entry private"). For this reason, the next stage must be specified in "firmware", not in "loadables". To support this additional functionality, and to properly model the boot process, where ATF runs before U-Boot, add the "os" properties and swap the firmware/loadable images in the FIT image. Since this description was copied as an example in commit 70248d6a2916 ("binman: Support generating FITs with multiple dtbs"), update those examples as well for correctness and consistency. Acked-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Use a macro for the BL31 load addressSamuel Holland2020-10-221-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This consolidates the SoC-specific part at the top of the file to avoid cluttering it up with preprocessor conditions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Provide a default BL31 filenameSamuel Holland2020-10-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use binman"), if the BL31 environment variable was not defined, the firmware would be loaded from a file "bl31.bin" in the current directory. Restore that behavior by providing that as the default filename in case no entry arg is provided, which will be the case if the environment variable is unset. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Fix spacing between nodesSamuel Holland2020-10-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Nodes should have a blank line separating them from sibling nodes and properties. Add the necessary lines. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | | reset: ast2500: Use SCU for reset controlChia-Wei, Wang2020-10-221-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | IPQ40xx: Add PRNG supportRobert Marko2020-10-221-0/+7
| | | | | | | | | | | | | | | | | | | | | Since we now have the driver for Qualcomm PRNG HW, lets use it and add the necessary clocks and nodes. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | IPQ40xx: Add support for MDIORobert Marko2020-10-221-0/+28
| | | | | | | | | | | | | | | | | | | | | Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | IPQ40xx: Add SPI supportRobert Marko2020-10-221-0/+12
| | | | | | | | | | | | | | | | | | | | | Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | | km: fix license string and compatible stringsHolger Brunck2020-10-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the ownership is now Hitachi Power Grids, change the license string and adapt the compatible string in DTS files. For kmeter1.dts we change it to "keymile,KMETER1" for now, as this is then compliant with what is submitted to the linux kernel. All other boards don't have a upstreamed version in linux mainline. Signed-off-by: Holger Brunck <holger.brunck@hitachi-powergrids.com> CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> CC: Heiko Schocher <hs@denx.de> CC: Marek Vasut <marex@denx.de> CC: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shWIP/20Oct2020Tom Rini2020-10-201-0/+1960
|\ \ \ | | | | | | | | | | | | - Assorted R-Car Gen3 updates
| * | | arm: dts: r8a774c0: Import DTS from Linux 5.9Lad Prabhakar2020-10-201-0/+1960
| |/ / | | | | | | | | | | | | | | | | | | | | | Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* | | arm: dts: mt8512: add usb related nodesChunfeng Yun2020-10-202-1/+82
|/ / | | | | | | | | | | | | Add usb, usb phy, and fixed regulators nodes Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
* | ARM: dts: sam9x60: use alphabetical orderClaudiu Beznea2020-10-191-14/+13
| | | | | | | | | | | | Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | ARM: dts: sam9x60: use CCF compatibles for PMCClaudiu Beznea2020-10-193-164/+33
| | | | | | | | | | | | | | Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | ARM: dts: sam9x60: use slow clock CCF compatible bindingsClaudiu Beznea2020-10-192-47/+20
| | | | | | | | | | | | | | | | Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | ARM: dts: sam9x60: use u-boot,dm-pre-relocClaudiu Beznea2020-10-191-0/+8
| | | | | | | | | | | | Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | ARM: dts: sam9x60ek: add clock frequencies to board fileClaudiu Beznea2020-10-192-2/+10
| | | | | | | | | | | | | | Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | Merge tag 'mmc-2020-10-14' of ↵WIP/15Oct2020Tom Rini2020-10-151-0/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
| * | arm: dts: lx2160ardb: support eMMC HS400 modeYangbo Lu2020-10-121-0/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Add properties related to eMMC HS400 mode. mmc-hs400-1_8v; bus-width = <8>; They had been already in kernel dts file since the first lx2160ardb dts patch. b068890 arm64: dts: add LX2160ARDB board support Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
* | arm64: dts: a3720: add support for espressobin with populated emmcAndre Heider2020-10-142-0/+45
| | | | | | | | | | | | | | | | Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for emmc, since our dtsi is still based on downstream and sdhc0 is used for the sd card. Signed-off-by: Andre Heider <a.heider@gmail.com>
* | arm64: dts: armada-3720-espressobin: split common parts to .dtsiAndre Heider2020-10-142-157/+174
| | | | | | | | | | | | | | | | | | Move most of the dts to the new common armada-3720-espressobin.dtsi file, just like Linux, but keep the current, downstream based, version. The dts itself is imported from Linux. Signed-off-by: Andre Heider <a.heider@gmail.com>
* | arm64: dts: armada-3720-espressobin: use Linux model/compatible stringsAndre Heider2020-10-141-2/+2
| | | | | | | | | | | | | | | | Fix the actual board vendor and ease synching dts files from Linux. Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: Initial iEi Puzzle-M801 supportLuka Kovacic2020-10-142-0/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial U-Boot support for the iEi Puzzle-M801 board based on the Marvell Armada 88F8040 SoC. Currently supported hardware: 1x USB 3.0 4x Gigabit Ethernet 2x SFP+ (with NXP PCA9555 and NXP PCA9544) 1x SATA 3.0 1x M.2 type B 1x RJ45 UART 1x SPI flash 1x EPSON RX8010 RTC Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
* | arm: dts: socfpga: arria10: Move to use generic handoff dtsiLey Foon Tan2020-10-093-330/+292
| | | | | | | | | | | | | | Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include the specify generated _handoff.h header file from qts-filter-a10.sh script. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMCDalon Westergreen2020-10-091-0/+305
| | | | | | | | | | | | | | | | Add the qts-filter-a10.sh generated handoff header file for the Arria10 SoCDK SDMMC u-boot device tree. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | arm: socfpga: Use DM watchdog timerChee Hong Ang2020-10-094-1/+9
|/ | | | | | | | | All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* Merge tag 'u-boot-amlogic-20201005' of ↵Tom Rini2020-10-0627-105/+786
|\ | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - generate unique mac address from SoC serial on S400 board - Add USB support for GXL and AXG SoCs - Update Gadget code to use the new GXL and AXG USB glue driver - Add a VIM3 board support to add dynamic PCIe enable in OS DT - Fix AXG pinmux with requesting GPIOs - Add missing GPIOA_18 for AXG pinctrl - Add Amlogic PWM driver
| * ARM: dts: sync amlogic G12A/SM1 DT from Linux 5.9-rc1Neil Armstrong2020-10-055-24/+373
| | | | | | | | | | | | | | | | | | | | This imports the G12A & SM1 SoC and boards DT changes from the Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: dts: meson-axg: add USB nodes for S400Neil Armstrong2020-10-052-0/+74
| | | | | | | | | | | | | | | | Add the correcly architectured USB Glue node for Meson AXG and the S400 board in -u-boot.dtsi until support in upstream Linux then backported. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * ARM: dts: sync amlogic AXG/GXL/GXM DT from Linux 5.8-rc1Neil Armstrong2020-10-0520-81/+339
| | | | | | | | | | | | | | | | | | This imports the AXG, GXL & GXM SoC and boards DT changes from the Linux commit b3a9e3b9622a ("Linux 5.8-rc1"). This change also removes GXL & GXM u-boot.dtsi hacks for USB gadget. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
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