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| | * | arm64: zynqmp: Correct value of shunt resistor for VCCINT and VCC_SOCSaeed Nowshadi2020-09-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Value of shunt resistor for INA226s that monitor VCCINT and VCC_SOC power rails are incorrect. This patch corrects those values. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
| | * | arm64: zynqmp: Add device tree node for 2nd mux on I2C1 busSaeed Nowshadi2020-09-231-0/+25
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1 ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and channel 2 is connected to J288 connector for QSFP1. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | binman: sunxi: Add help message for missing sunxi ATF BL31Simon Glass2020-09-221-0/+1
| | | | | | | | | | | | | | | | | | Add a special help message pointing to the relevant README. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sunxi: Convert 64-bit boards to use binmanSimon Glass2020-09-221-1/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present 64-bit sunxi boards use the Makefile to create a FIT, using USE_SPL_FIT_GENERATOR. This is deprecated. Update sunxi to use binman instead. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | Merge branch 'master' into nextTom Rini2020-09-215-8/+14
| |\ \ | | |/ | | | | | | Merge in v2020.10-rc5
| * | IPQ40xx: Add USB nodesWIP/2020-09-18-improve-ipq40xx-supportRobert Marko2020-09-181-0/+76
| | | | | | | | | | | | | | | | | | | | | There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | IPQ40xx: Add reset controller supportRobert Marko2020-09-181-0/+9
| | | | | | | | | | | | | | | | | | | | | Since we have a driver for the reset controller, lets add the necessary node. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | IPQ40xx: Add SMEM supportRobert Marko2020-09-181-0/+5
| | | | | | | | | | | | | | | | | | | | | There is already existing driver for SMEM so lets enable it for IPQ40xx as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | IPQ40xx: clk: Use dt-bindings instead of hardcodingRobert Marko2020-09-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Its common to use dt-bindings instead of hard-coding clocks or resets. So lets use the imported Linux GCC bindings on IPQ40xx target. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | Merge tag 'ti-v2021.01-next' of ↵WIP/15Sep2020-nextTom Rini2020-09-157-1/+212
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next - Hyperflash boot for J7200 - Update Main R5FSS lockstep mode - R5F remoteproc support for J7200 - Minor env fixes - Add SPI boot support for am335x-icev2
| | * | arm: dts: am335x-icev2: Add spi nodeFaiz Abbas2020-09-151-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | Add spi and spi nor flash nodes for am335x-icev2. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
| | * | arm: dts: k3-j7200-r5: Add fs_loader nodeSuman Anna2020-09-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a generic fs_loader node to the K3 J7200 R5 common board dts file and use it as the chosen firmware-loader so that it can be used for loading various firmwares from a boot media/filesystem in R5 SPL on K3 J7200 EVM. Signed-off-by: Suman Anna <s-anna@ti.com>
| | * | arm: dts: k3-j7200-main: Add MAIN domain R5F cluster nodesSuman Anna2020-09-152-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster is present within the MCU domain (MCU_R5FSS0), and the other one is present within the MAIN domain (MAIN_R5FSS0). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory. Add the DT node for the MAIN domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com>
| | * | arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster nodeSuman Anna2020-09-152-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster is present within the MCU domain (MCU_R5FSS0), and the other one is present within the MAIN domain (MAIN_R5FSS0). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: Suman Anna <s-anna@ti.com>
| | * | arm: dts: k3-j721e-main: Configure MAIN R5FSS1 for Split-modeSuman Anna2020-09-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the default so that two different applications can be run on each of the R5F cores in performance mode. LockStep-mode would be available only on SoCs efused with the appropriate bit, and Split-mode is the mode that is available on all J721E SoCs. Signed-off-by: Suman Anna <s-anna@ti.com>
| | * | ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlashVignesh Raghavendra2020-09-152-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | Enable HyperBus and HyperFlash to support HyperFlash boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | | arm: dts: fix ast2500-evb inclusion for the correct soc familyThirupathaiah Annapureddy2020-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Include ast2500-evb.dtb for CONFIG_ASPEED_AST2500 instead of for all aspeed targets. ast2400 is based on ARM926EJ-S processor (ARMv5-architecture). ast2500 is based on ARM1176JZS processor (ARMv6-architecture). ast2600 is based on Cortex A7 processor (ARMv7-A architecture). Each of the above SOC is using a different ARM CPU(s) with different ARM architecture revision. It is not possible to support all 3 of these families in a single binary. So there is no need to build ast2500-evb.dtb for other SOC families. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
| * | | cosmetic: aspeed: Modify for SPDX-LicenseRyan Chen2020-09-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify SPDX-License for furture patch warning Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
| * | | clock:aspeed: Sync with Linux kernel clock header defineRyan Chen2020-09-091-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
| * | | cosmetic: aspeed: ast2500: Rename clock headerRyan Chen2020-09-091-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
* | | ARM: dts: stm32: Add missing dm-spl props for SPI NOR on AV96Marek Vasut2020-10-021-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The u-boot,dm-spl DT props are missing on AV96, hence the pinmux and flash0 nodes are not included in the reduced SPL DT. This prevents SPI NOR boot from working at all. Fix this by filling them in. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | arm: dts: lx2160a: Add IO rangeWasim Khan2020-09-241-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add IO range property to fix below error on uboot PCI: Failed autoconfig bar 18 Signed-off-by: Wasim Khan <wasim.khan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | armv8: dts: fsl-lx2160a: add gpio0 gpio1 gpio3 DT nodeshui.song2020-09-241-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | add gpio0 gpio1 gpio3 DT nodes to fsl-lx21600.dtsi Signed-off-by: hui.song <hui.song_1@nxp.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | arm64: Layerscape: Survive LPI one-way reset workaroundHou Zhiqiang2020-09-244-0/+24
| |/ |/| | | | | | | | | | | | | | | | | | | The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | apalis-imx8qm: rename all occurences to apalis-imx8Philippe Schenker2020-09-171-3/+3
| | | | | | | | | | | | | | | | The Toradex product is called apalis-imx8 consisting of SoM with i.MX8QM and i.MX8QP SoCs. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
* | colibri-imx8qxp: rename all occurences to colibri-imx8xPhilippe Schenker2020-09-171-3/+3
| | | | | | | | | | | | | | | | The Toradex product is called colibri-imx8x consisting of SoM with i.MX8QXP and i.MX8DX SoCs. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
* | rockchip: rv1108: Enable grf as pre-reloc nodeKever Yang2020-09-161-0/+4
| | | | | | | | | | | | The grf node will be used before relocate, enable it in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | ARM: dts: stm32: Adjust PLL4 settings on AV96 againMarek Vasut2020-09-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the 50 MHz generated from PLL4Q cannot be divided well enough to produce accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz, which is in tolerance for the SDMMC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Gerald Baeza <gerald.baeza@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | ARM: dts: stm32: Pull UART4 RX high on AV96Marek Vasut2020-09-091-0/+2
|/ | | | | | | | | | | | | There is no dedicated pull resistor on the AV96 UART4 (console UART) pin. In case there is no UART adapter installed on the AV96, the line is floating and can trigger reception of garbage characters, which in turn can abort U-Boot autoboot. Add default pull up to mitigate this problem. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* Merge tag 'ti-v2020.10-rc4' of ↵WIP/31Aug2020Tom Rini2020-08-311-6/+6
|\ | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Update to ABI 3.0 - Fix i2c write in eeprom driver
| * arm: dts: k3-am65: Update the RM resource typesLokesh Vutla2020-08-311-6/+6
| | | | | | | | | | | | | | Update the ringacc and udma dt nodes to use the latest RM resource types similar to the ones used in k3-j721e dt nodes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | arm: dts: a37x0: enable sd card support on espressobinWilson Ding2020-08-311-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled SDIO slot 0 (south bridge) for SD card on Espressobin board. Change-Id: I51a2debf9fba276b9c4a2bc6da91328d47f443e3 Signed-off-by: Wilson Ding <dingwei@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60945 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> [pali: Define cd-gpios and enable CONFIG_DM_REGULATOR_GPIO] Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
* | arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DTPali Rohár2020-08-313-3/+3
| | | | | | | | | | | | | | | | | | | | | | Change active-high to active-low and change DT property name from reset-gpio to reset-gpios. This format of gpio reset is used by pci-aardvark driver in Linux kernel. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
* | arm64: dts: armada-3720-espressobin: fix COMPHY nodesMarek Behún2020-08-311-4/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes initialization of COMPHY on EspressoBin. Commit 22f418935be4 ("phy: marvell: a3700: Use comphy_mux on Armada 37xx.") introduced usage of comphy_mux on Armada 37xx comphy driver. The lanes are defined in comphy_a3700.c as described in functional specification, that is: lane 0 is SGMII1 or USB3 lane 1 is PCIe or SGMII0 lane 2 is SATA or USB3 But the DTS for EspressoBin configures PCIe on lane 0 and USB3 on lane 1, which is wrong in the sense of the specification and doesn't work with the comphy_mux code, which is 2 years now (the aardvark driver causes synchronous abort in U-Boot). It worked till the above mentioned commit, because the code for powering up PCIe PHY doesn't work with lane number at all, and the code for powering up USB3 PHY works differently only if USB3 is on lane 2, ie. the check goes like: if (lane == 2) something else something else so it does not differentiate between lanes 0 and 1. In the future I shall post patches that remove the comphy_a3700 driver and add comphy driver which uses calls to ATF, like Linux' driver does. This will have the advantage of same DTS bindings as Linux', but till this is done, we need this patch. Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Pali Rohár <pali@kernel.org> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
* Merge tag 'u-boot-rockchip-20200820' of ↵Tom Rini2020-08-251-0/+13
|\ | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix rk3399 evb sdcard support - Fix for SPL_LED support
| * rockchip: dts: rk3399-evb: add sdmmc nodeKever Yang2020-08-211-0/+13
| | | | | | | | | | | | | | | | The sdmmc node is missing after the dts sync patch: 167efc2c7a arm64: dts: rk3399: Sync v5.7-rc1 from Linux But we still need it for boot from SD card, so add it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | arm: dts: mt7623: add USB nodesFrank Wunderlich2020-08-242-0/+62
| | | | | | | | | | | | | | This adds USB nodes for MT7623/BPI-R2 Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
* | arm: dts: mt7622: add USB nodesFrank Wunderlich2020-08-243-0/+72
| | | | | | | | | | | | | | Add DTS nodes for MT7622/BPI-R64 Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
* | arm: dts: rename mt7622-bpi-r64.dtsFrank Wunderlich2020-08-242-1/+1
| | | | | | | | | | | | | | rename mt7622-bpi-r64.dts to mt7622-bananapi-bpi-r64.dts to follow naming convensions Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* | board: armltd: Add support for Total Compute platformUsama Arif2020-08-242-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | Total Compute is based on ARM architecture and has the following features enabled in u-boot: - PL011 UART - PL180 MMC - NOR Flash - FIT image with Signature - AVB Signed-off-by: Usama Arif <usama.arif@arm.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'xilinx-for-v2020.10-rc3' of ↵WIP/20Aug2020Tom Rini2020-08-2024-40/+40
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.10-rc3 - Fix fdtfile variable setup - Fix bootm_*/fdt_high/initrd_high variables handling - Fix Kconfig dependencies for Xilinx drivers - Fix booting u-boot from lowest memory - Fix firmware payload argument count for Versal - Fix dfu configurations - Fix mio_bank property handling - Fix and align code around ID detection - Start to use ENV_VARS_UBOOT_RUNTIME_CONFIG - Simplify logic around reading MAC from eeprom - Decrease malloc length for zynqmp mini qspi - Enable preboot for ZynqMP and Versal i2c: - Fix i2c eeprom partitions handling mmc: - Fix logic around HS mode enabling and use proper functions
| * xilinx: Fix xlnx,mio_bank propertyMichal Simek2020-08-2022-29/+29
| | | | | | | | | | | | | | | | | | | | | | s/xlnx,mio_bank/xlnx,mio-bank/g DT binding is describing mio-bank not mio_bank that's why fix all DTSes and also driver itself. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Peng Fan <peng.fan@nxp.com>
| * i2c: eeprom: Use reg property instead of offset and sizeMichal Simek2020-08-202-11/+11
| | | | | | | | | | | | | | | | Remove adhoc dt binding for fixed-partition definition for i2c eeprom. fixed-partition are using reg property instead of offset/size pair. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | dts: r64: add sata- and asm_sel nodesWIP/2020-08-19-mediatek-updatesFrank Wunderlich2020-08-192-0/+41
| | | | | | | | | | | | | | | | | | | | | | asm_sel is for switching between sata and pcie mode on r64 there is GPIO90 connected to ASM1480 which switches RX/TX pairs to PCIe/SATA connector output-low means sata-controller is active with 2020-10 now reg is also needed for the phy itself Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* | arm: dts: mt7622: add PCIe nodes for BananaPi-R64Frank Wunderlich2020-08-191-0/+31
| | | | | | | | | | | | | | | | this patch adds PCIe-Nodes for BananaPi R64 original nodes from Chuanjia Liu for mt7622-rfb Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* | dts: r64: add r64 dtsFrank Wunderlich2020-08-192-0/+207
| | | | | | | | | | | | add a separate DTS for BananaPi R64 because it has 1GB RAM and SATA-Support Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* | arm: dts: add watchdog-node for mt7622Frank Wunderlich2020-08-191-0/+5
| | | | | | | | | | | | adding a watchdog-node to mt7622 dtsi Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
* | arm: dts: mediatek: add PCIe node for MT7622Chuanjia Liu2020-08-192-0/+103
| | | | | | | | | | | | | | This patch adds PCIe node in dts for Mediatek MT7622 Soc. Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Signed-off-by: Henry Yen <henry.yen@mediatek.com>
* | arm: dts: mediatek: add pciesys support for MT7622 SoCChuanjia Liu2020-08-191-0/+7
|/ | | | | | | This patch adds pciesys support in dts for MediaTek MT7622 SoC. Signed-off-by: Henry Yen <henry.yen@mediatek.com> Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
* ARM: dts: uniphier: resync DT with Linux 5.9-rc1Masahiro Yamada2020-08-1818-61/+235
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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