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* Merge tag 'xilinx-for-v2021.10-rc3' of ↵WIP/27Aug2021Tom Rini2021-08-2713-36/+80
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.10-rc3 xilinx: - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY - Print information about cpu via soc drivers and enable DISPLAY_CPUINFO - Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT zynq: - Wire single QSPI - Use power-source instead of io-standard properties - Enable nor on zc770-xm012 zynqmp: - Change handling around multi_boot() - Setup offset for u-boot.itb in spi - Generate run time dfu_alt_info for capsule update - Use explicit values for enums (zynqmp_firmware.h) - Enable RTC/SHA1/BUTTON/BUTTON_GPIO command - Disable WDT driver by default - Bind usb/scsi via preboot because of EFI - DT updates/fixes - Add soc driver - Fix SPL SPI boot mode versal: - Add soc driver sdhci: - Update tap delay programming for zynq_sdhci driver cmd: - Fix RTC uclass handling in date command - Update pwm help message - Update reset help message watchdog: - Fix wwdt compilation rtc: - Deal with seq alias in rtc uclass - Add zynqmp RTC driver fdt: - Add kernel-doc for fdt_fixup_memory_banks()
| * xilinx: common: Enabling generic function for DT reselectionMichal Simek2021-08-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot support board detection at run time and based on it change DT. This feature is implemented for SOM Kria platforms which contain two eeproms which contain information about SOM module and CC (Carrier card). Full U-Boot starts with minimal DT file defined by CONFIG_DEFAULT_DEVICE_TREE which is available in multi DTB fit image. It is using default setup of board_name variable initializaed to DEVICE_TREE which corresponds to CONFIG_DEFAULT_DEVICE_TREE option. When DTB_RESELECT is enabled board_detection() is called. Keep it your mind that this code is called before relocation. board_detection() is calling xilinx_read_eeprom() which fills board_info (xilinx_board_description) structure which are parsed in board_name_decode(). Based on DT configuration and amount of nvmemX aliases name of the board is composed by concatenating CONFIG_SYS_BOARD "-" <board_name> "-rev" <board_revision> "-" <cc_name> "-rev" <cc_revision>. If CC is not present or more are available it keeps going. When board name is composed and returned from board_name_decode() it is assigned to board_name variable which is used by board_fit_config_name_match() which is called via fdtdec_setup() when it goes over config options in multi dtb FIT image. From practical point of view multi DTB image is key point here which has to contain configs for detected combinations. Unfortunately as of now they have to be full DTBs and DTBOs are not supported. That's why configuration like: config_X { description = "zynqmp-board-cc"; fdt = "board", "cc"; }; needs to be squashed together with: fdtoverlay -o zynqmp-board-cc -i arch/arm/dts/zynqmp-board.dtb \ arch/arm/dts/zynqmp-cc.dtbo and only one dtb is in fit: config_X { description = "zynqmp-board-cc"; fdt = "board-cc"; }; For creating multi DTBs fit image use mkimage -E, e.g.: mkimage -E -f all.its all.dtb When DTB_RESELECT is enabled xilinx_read_eeprom() is called before relocation and it uses calloc for getting a buffer. Because this is dynamic memory it is not relocated that's why xilinx_read_eeprom() is called again as the part of board_init(). This second read with calloc buffer placed in proper position board_late_init_xilinx() can setup u-boot variables as before. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: dts: Make sure that all DTBs are 64bit alignedMichal Simek2021-08-261-1/+1
| | | | | | | | | | | | | | Start of DTB should be 64bit aligned that's why also make sure that end is also 64bit aligned. It is not required but it is nice thing to do. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Enable smcc and nor for zc770-xm012Michal Simek2021-08-261-0/+9
| | | | | | | | | | | | Enable cfi flash on zc770-xm012 configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Wire single qspi on couple of boardsMichal Simek2021-08-264-0/+32
| | | | | | | | | | | | Single configuration is working fine and no issue to enable it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Replace 'io-standard' with 'power-source' propertySai Krishna Potthuri2021-08-262-20/+20
| | | | | | | | | | | | | | | | Replace 'io-standard' property with 'power-source' property in all zynq dts files to be in sync with Zynq Pinctrl driver. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)Raju Kumar Pothuraju2021-08-264-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing "jedec, spi-nor" compatible string for QSPI flash node. Spi-nor framework uses this compatibility string to probe & initialize flash. With missing compatibility string we are observing below error: Zynq> sf probe 0 0 0 jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes: 00, 00, 00 Failed to initialize SPI flash at 0:0 (error -2) Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Update comment style sm-k26Michal Simek2021-08-261-1/+1
| | | | | | | | | | | | Trivial style patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Fix header alignment on kv260 boardsMichal Simek2021-08-262-8/+8
| | | | | | | | | | | | Fix header alignment. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Fix node name for ds35/36 ledsMichal Simek2021-08-261-2/+2
| | | | | | | | | | | | By dt-binding specs led nodes should have -led suffix that's why add it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm: dts: Add base dtsi and devkit dts for Intel N5X deviceSiew Chin Lim2021-08-254-0/+377
| | | | | | | | | | | | | | | | Add device tree for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
* | board: sl28: drop unneeded and outdated flash partitionsMichael Walle2021-08-181-55/+0
| | | | | | | | | | | | | | | | | | This board doesn't use the MTD subsystem in u-boot, thus there is no need to specify the partitions. They are outdated anyway. Just drop them. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHzMarek Vasut2021-08-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, which causes additional signal delay. At 108 MHz, this delay triggers a sporadic issue where the first bit of RX data is not received by the QSPI controller. There are two options of addressing this problem, either by using the DLYB block to compensate the extra delay, or by reducing the QSPI bus clock frequency. The former requires calibration and that is overly complex for SPL, so opt for the second option. This incurs 20ms delay during boot, when SPL loads U-Boot to DRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | arm: dts: stm32mp15: alignment with v5.14Patrick Delaunay2021-08-163-9/+42
| | | | | | | | | | | | | | | | | | | | | | Device tree alignment with Linux kernel v5.14-rc3 - ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15 - ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151 - ARM: dts: stm32: add a new DCMI pins group on stm32mp15 - ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | arm: stm32mp: add defconfig for trusted boot with FIPPatrick Delaunay2021-08-162-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TF-A FIP support for trusted boot on STM32MP15x, when STM32MP15x_STM32IMAGE is not activated. With FIP support the SSBL partition is named "fip" and its size is 4MB, so the ENV partition name in device tree (for SD card or eMMC) or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_REDUND) need to be modified. With FIP the TEE MTD partitions are removed because the OP-TEE binray are included in the FIP containers. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | arm: stm32mp: handle the OP-TEE nodes in DT with FIP supportPatrick Delaunay2021-08-162-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With FIP support in TF-A (when CONFIG_STM32MP15x_STM32IMAGE is not activated), the DT nodes needed by OP-TEE are added by OP-TEE firmware in U-Boot device tree, present in FIP. These nodes are only required in trusted boot, when TF-A load the file u-boot.stm32, including the U-Boot device tree with STM32IMAGE header, in this case OP-TEE can't update the U-Boot device tree. Moreover in trusted boot mode with FIP, as the OP-TEE nodes are present in U-Boot device tree only when needed the function stm32_fdt_disable_optee can be removed. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | rockchip: px30: add support for SFC for Odroid Go AdvanceChris Morgan2021-08-122-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | The Odroid Go Advance uses a Rockchip Serial Flash Controller with an XT25F128B SPI NOR flash chip. This adds support for both. Note that while both the controller and chip support quad mode, only two lines are connected to the chip. Changing the pinctrl to bus2 and setting tx and rx lines to 2 for this reason. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | rockchip: px30: add the serial flash controllerChris Morgan2021-08-121-0/+38
| | | | | | | | | | | | | | | | Add the serial flash controller to the devicetree for the PX30. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm: dts: sync the Rockhip 3368 SoCs from LinuxPeter Robinson2021-08-125-220/+118
| | | | | | | | | | | | | | Sync the rk3368 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm: dts: sync the Rockhip 3328 SoCs from LinuxPeter Robinson2021-08-1210-258/+487
| | | | | | | | | | | | | | Sync the rk3328 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm: dts: sync the Rockhip 3399 SoCs from LinuxPeter Robinson2021-08-1225-447/+871
| | | | | | | | | | | | | | | | Sync the rk3399 DTs and associated bits from 5.14-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> (Remove the conflict content for vmarc-som) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: rk3399: r4s: Remove undesirable MAC address fetching methods for ethernetXiaobo Tian2021-08-111-15/+0
| | | | | | | | | | | | | | | | Remove the recommended MAC address from the network card. NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which stores the MAC address. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: rk3399: r4s: Inheritance uses the sdmmc definition in dtsiXiaobo Tian2021-08-111-4/+0
| | | | | | | | | | | | | | | | The host-index-min property is invalid, so it inherits from the sdmmc definition in dtsi. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm64: rk3399: r4s: correct the LEDS label nameXiaobo Tian2021-08-111-3/+2
| | | | | | | | | | | | | | | | Correct the LEDS label name and remove the board type prefix, which is actually unnecessary here, removes the redefined system status LED pin. Signed-off-by: Xiaobo Tian <peterwillcn@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | ARM: dts: rockchip: update rk3188-radxarock.dtsJohan Jonker2021-08-112-53/+73
| | | | | | | | | | | | | | | | | | | | | | In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | ARM: dts: rockchip: update rk3188.dtsiJohan Jonker2021-08-112-136/+356
| | | | | | | | | | | | | | | | | | | | | | In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | ARM: dts: rockchip: update rk3xxx.dtsiJohan Jonker2021-08-114-74/+181
| | | | | | | | | | | | | | | | | | | | In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. This file has recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3xxx-u-boot.dtsi file. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | arm: imx: add i.MX8ULP EVK supportPeng Fan2021-08-093-0/+266
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | arm: dts: add i.MX8ULP dtsiPeng Fan2021-08-092-0/+1706
| | | | | | | | | | | | Add i.MX8ULP dtsi Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | mx28evk: Convert to driver modelFabio Estevam2021-08-092-0/+11
| | | | | | | | | | | | | | | | | | | | | | Make the conversion to driver model as it is mandatory. Successfully tested booting Linux from the SD card. Dropped support for networking and splash screen as these need to be properly converted to DM and tested. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* | board: ge: bx50v3: Add PCIe reset to DTSebastian Reichel2021-08-091-0/+10
| | | | | | | | | | | | | | Add PCIe reset gpio to the Bx50v3 devicetree and get get rid of CONFIG_PCIE_IMX_PERST_GPIO. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
* | board: gateworks: venice: add imx8mm-gw7902 supportTim Harvey2021-08-093-0/+1008
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring: - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller - LTE CAT M1 modem - USB 2.0 HUB - M.2 Socket with USB2.0, PCIe, and dual-SIM - IMX8M FEC - PCIe based GbE - RS232/RS485/RS422 serial transceiver - GPS - CAN bus - WiFi / Bluetooth - MIPI header (DSI/CSI/GPIO/PWM/I2S) - PMIC Do the following to add support for it: - add dts - add PMIC config Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | arm: dts: imx8mm-venice-gw7901: use common u-boot dtsiTim Harvey2021-08-091-34/+1
| | | | | | | | | | | | Use the common imx8mm-u-boot.dtsi Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | arm: dts: imx8mm-venice-gw700x: fix fifo-depth phy propsTim Harvey2021-08-091-2/+1
| | | | | | | | | | | | | | | | Replace the deprecated 'tx-fifo-depth' and 'rx-fifo-depth' properties not supported by U-Boot drivers/net/phy/dp83867.c with the proper 'ti,fifo-depth' property. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | arm: dts: imx8mm-venice-gw71xx: fix USB OTG VBUSTim Harvey2021-08-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The GW71xx has a USB Type-C connector with USB 2.0 signaling. GPIO1_12 is the power-enable to the TPS25821 Source controller and power switch responsible for monitoring the CC pins and enabling VBUS. Therefore GPIO1_12 must always be enabled and the vbus output enable from the IMX8MM can be ignored. To fix USB OTG VBUS enable a pull-up on GPIO1_12 to always power the TPS25821 and change the regulator output to GPIO1_10 which is unconnected. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: remove hard-coded USB OTG pinmuxTim Harvey2021-08-094-0/+4
| | | | | | | | | | | | | | pinmux is now done via dt. Add missing OTG_OC pinmux for boards that use it. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx: ventana: fix UMS supportTim Harvey2021-08-0912-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Gateworks Ventana boards have always had usb0=usbh1 and usb1=usbotg because OTG is often subloaded on these boards and a bit in the EEPROM which flagging that OTG is subloaded is used to remove the dt node via the alias. U-Boot DM_USB UMS requires the usb0 alias be assigned to the usbotg so fix the usb0 alias in order for UMS to work. Fixes 72c46327f03f: ("imx: ventana: enable dm support for USB") Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | imx28-evk: Import devicetree file from LinuxFabio Estevam2021-08-061-0/+360
|/ | | | | | | | | | Import the imx28-evk devicetree files from Linux kernel version 5.11-rc7. This is in preparation for converting the mx28evk_defconfig target to driver model. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-samsungTom Rini2021-08-031-0/+1
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| * samsung: exynos: Convert SROMC interface to a driverSimon Glass2021-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add a bus driver for this and use it to configure the bus parameters for the Ethernet interface. Drop the old pre-driver-model code. Switch over to use driver model for Ethernet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2021-07-311-2/+2
|\ \ | | | | | | | | | | | | | | | | | | - Move the PSCI runtime code for H3/A23/A33 into SRAM - Pick the environment from the actual MMC boot device (SD card vs. eMMC) - Plus a small improvement from Icenowy, just for good measure.
| * | sunxi: decide the inclusion of SCP by SCP_ADDR existenceIcenowy Zheng2021-08-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are more Allwinner SoCs that do not have a SCP now. When there's no SCP_ADDR macro defined, we can assume there's no SCP available. Drop the scp part of FIT description when SCP_ADDR does not exist. Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Merge tag 'ti-v2021.10-rc2' of ↵Tom Rini2021-07-2916-233/+726
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Add MMC High speed modes for AM64 and J7200 - Add Sierra/Torrent SERDES driver - Minor clean-ups for R5F boot from SPL
| * | arm: dts: k3-j721e-r5: Remove MAIN R5FSS0 cluster from SPLSuman Anna2021-07-272-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MAIN R5FSS0 cluster and corresponding nodes are no longer required to be enabled in R5 SPL after removing the support for booting any core from this cluster on R5 SPL. So, remove these from the relevant dts files. This is essentially a revert of the additions done in commit 2984b82b3b76 ("arm: dts: k3-j721e-r5: Enable r5fss0 cluster in SPL"). Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210726211311.5977-5-s-anna@ti.com
| * | arm: dts: k3-am65: Fix up MCU R5FSS cluster mode back to Split-modeSuman Anna2021-07-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default U-Boot environment variables and design are all set up to have the MCU R5FSS cluster to be in Split-mode. This is the setting in v2021.01 U-Boot and the dt nodes are synched with the kernel binding property names in commit 468ec2f3ef8f ("remoteproc: k3_r5: Sync to upstreamed kernel DT property names") merged in v2021.04-rc2. The mode for the cluster got switched back to LockStep mode by mistake in commit e49787634312 ("arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-Boot") also in v2021.04-rc2. This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f@41400000: Invalid op: Trying to start secondary core 2 in lockstep mode Load Remote Processor 1 with data@addr=0x82000000 65268 bytes: Failed! Fix this by switching back the cluster to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes: e49787634312 ("arm: dts: k3-am65: Sync Linux v5.11-rc6 dts into U-Boot") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210726162213.28719-1-s-anna@ti.com
| * | arch: dts: am642-sk-u-boot: Disable main_sdhci0 DT node and define alias ↵Aswath Govindraju2021-07-271-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | index 1 for main_sdhci1 node A Wilink wireless device is connected to MMCSD0 subsystem and is not supported in U-Boot. Therefore, disable main_sdhci0 device tree node in U-Boot. If main_sdhci0 device tree node is disabled then the the index of main_sdhci1 node becomes 0 which leads to break in boot flow. Therefore, add an alias to fix the index to 1. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210726152807.22991-3-a-govindraju@ti.com
| * | arm: dts: k3-j7200-common-proc-board-u-boot: Add u-boot tags for torrent serdesAswath Govindraju2021-07-271-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add u-boot tags for torrent serdes. This has properties specific to u-boot on top of DT in v5.13 Linux Kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-15-kishon@ti.com
| * | arm: dts: k3-j7200-common-proc-board: Enable SERDES DTAswath Govindraju2021-07-271-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add default lane function for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-14-kishon@ti.com
| * | arm: dts: k3-j7200-main: Add DT node for torrent serdesAswath Govindraju2021-07-271-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add DT node for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-13-kishon@ti.com
| * | ARM: dts: k3-j721e: Add support for USB3 in USB0 instanceKishon Vijay Abraham I2021-07-271-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the parent clock of wiz3_pll0_refclk to the internal clock required for USB3 to be functional and also remove "ti,usb2-only" property as it now supports USB3 mode. This has properties specific to u-boot on top of DT present in v5.13 of Linux Kernel. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-12-kishon@ti.com
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