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* sunxi: dts: sync Allwinner V3s-related DTs from Linux 5.10-rc1Icenowy Zheng2020-11-176-30/+725
| | | | | | | | This commit imports device tree files that are related to Allwinner V3 series from Linux commit 3650b228f83a ("Linux 5.10-rc1"). Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* sunxi: DT: A64: update device tree filesSamuel Holland2020-11-1725-631/+2383
| | | | | | | | | | | | | Import updated device trees from Linux tag v5.9. This picks up new hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI files for the Pinebook and the Teres-I, since the ANX6345 bridge is now supported upstream. A couple of headers needed updates for recently-added hardware support. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge tag 'ti-v2021.01-rc3' of ↵Tom Rini2020-11-164-1/+259
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Fix Nokia RX-51 boot issues - Fix CONFIG_LOGLEVEL on K3 devices - Add phyBOARD REGOR support
| * ARM: am335x: Add phyBOARD REGOR supportParthiban Nallathambi2020-11-154-1/+259
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | phyBOARD-REGOR is based on phyCORE AM335x R2 SoM (PCL060). CPU : AM335X-GP rev 2.1 Model: Phytec AM335x phyBOARD-REGOR DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 eth0: ethernet@4a100000 Working: - Eth0 - i2C - MMC/SD - NAND - UART - USB (host) Device trees were taken from Linux mainline: commit c4d6fe731176 ("Linux 5.9.0") Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'u-boot-amlogic-20201116' of ↵Tom Rini2020-11-166-4/+24
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Clock fix MMC driver for SM1 based platforms - sync SOC Ids from Linux 5.10-rc1 - fix potential build warning on meson_dw_hdmi and meson-g12a-usb2 phy
| * | ARM: dts: meson-sm1: add u-boot specific MMC controller compatibleNeil Armstrong2020-11-126-4/+24
| |/ | | | | | | | | | | | | | | | | | | In order to enable the Amlogic SM1 MMC controller fix, we need to add a u-boot specific MMC controller compatible. This adds a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi to use this for SM1 based boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | rockchip: rockpro64: fix boot from SPI flash on spi1Hugh Cole-Baker2020-11-131-4/+0
|/ | | | | | | | | | | | | | | | | Commit c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") added an alias spi1 referring to spi@ff1d0000, however there was already an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and having both aliases present broke booting from SPI flash for this board. Remove the spi0 alias, set the default bus for SPI flash to 1, and enable support for numbered aliases in SPL so that it uses the same bus numbering as U-Boot proper. This fixes booting from U-Boot in SPI flash on the rockpro64 board. Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com> Suggested-by: Simon Glass <sjg@chromium.org> Fixes: c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob") Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-11-067-0/+153
|\ | | | | | | | | | | | | | | | | - Add a new SMBIOS parser and enable it when booting from coreboot - Fix up various driver names to avoid dtoc warnings - Fully enable ACPI support on Google Chromebook Coral - Add a way to set SMBIOS properties using the devicetree - Update existing boards to use devicetree for SMBIOS using a new default sysinfo driver
| * arm64: mvebu: Use devicetree for SMBIOS settings on uDPUSimon Glass2020-11-061-0/+20
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * odroid-c2: Use devicetree for SMBIOS settingsSimon Glass2020-11-061-0/+23
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * imx: Use devicetree for SMBIOS settings on MYiR MYS-6ULXSimon Glass2020-11-061-0/+25
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * rockchip: Use devicetree for SMBIOS settingsSimon Glass2020-11-064-0/+85
| | | | | | | | | | | | | | | | Add settings and enable the default sysinfo driver so that these can come from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge tag 'u-boot-imx-20201105' of ↵Tom Rini2020-11-055-0/+1019
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx for 2021.1 --------------------- - new boards : GE (new B1x5v2), phytec phyCORE-i.MX8MM - converted doc to reST - fixes for verdin-imx8mm (Toradex) - fixes for i.MX thermal driver - mx7ulp: Align the PLL_USB frequency - mx53: primary/secondary bmode Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/741465284
| * board: ge: b1x5v2: Add GE B1x5v2 and B1x5Pv2Sebastian Reichel2020-11-012-0/+655
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GE B1x5v2 patient monitor series is similar to the CARESCAPE Monitor series (GE Bx50). It consists of a carrier PCB used in combination with a Congatec QMX6 SoM. This adds U-Boot support using device model everywhere and SPL for memory initialization. Proper configuration is provided as 'ge_b1x5v2_defconfig' and the combined image u-boot-with-spi.imx can be flashed directly to 1024 byte offset to /dev/mtdblock0. Alternatively SPL and u-boot.imx can be loaded separately via USB-OTG using e.g. imx_usb. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM supportTeresa Remmet2020-11-013-0/+360
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
| * dts: Provide LED DTS description for HSC and DDC imx53 devicesLukasz Majewski2020-11-011-0/+4
| | | | | | | | | | | | Those two LEDs are used to indicate U-Boot's boot stage. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* | Merge tag 'u-boot-atmel-fixes-2021.01-a' of ↵WIP/02Nov2020Tom Rini2020-11-029-9/+9
|\ \ | |/ |/| | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel fixes for 2021.01 cycle: This specific feature set includes the patches for DT required to fix the warnings for newer DTC version (1.6.0+), i2c and spi bus unit address.
| * ARM: dts: at91: sama5d3xmb_cmp: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: sam9260ek: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9260ek.dtb.pre.tmp:119.21-123.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: sama5d3xmb: fix I2C bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/sama5d3xmb.dtsi:64.25-83.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f0018000/camera@0x30: I2C bus unit address format error, expected "30" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: gurnard: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9g45-gurnard.dtb.pre.tmp:118.21-122.7: Warning (spi_bus_reg): /ahb/apb/spi@fffa4000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: at91sam9g25ek: fix I2C bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9g25ek.dtb.pre.tmp:28.25-47.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8010000/camera@0x30: I2C bus unit address format error, expected "30" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: at91sam9g20ek_common: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/at91sam9g20ek_common.dtsi:100.21-104.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: at91sam9g20-taurus: fix SPI bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9g20-taurus.dtb.pre.tmp:79.18-83.4: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/mtd_dataflash@0: SPI bus unit address format error, expected "1" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: at91sam9261ek: fix SPI unit address warningEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91sam9261ek.dtb.pre.tmp:124.15-144.7: Warning (spi_bus_reg): /ahb/apb/spi@fffc8000/tsc2046@0: SPI bus unit address format error, expected "2" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: vinco: fix I2C warning bus unit addressEugen Hristev2020-11-021-1/+1
| | | | | | | | | | | | w+arch/arm/dts/.at91-vinco.dtb.pre.tmp:131.18-134.7: Warning (i2c_bus_reg): /ahb/apb/i2c@f8024000/rtc@64: I2C bus unit address format error, expected "32" Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* | Merge tag 'u-boot-rockchip-20201031' of ↵WIP/30Oct2020Tom Rini2020-10-3010-11/+344
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New PX30 board: Engicam PX30.Core; - Fix USB HID support for rock960; - Remove host endianness dependency for rockchip mkimage; - dts update for rk3288-tinker; - Enable console MUX for some ROCKPi boards; - Add config-based ddr selection for px30;
| * | rockchip: Add Engicam PX30.Core C.TOUCH 2.0Jagan Teki2020-10-302-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0Jagan Teki2020-10-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | rockchip: Add Engicam PX30.Core EDIMM2.2 Starter KitJagan Teki2020-10-302-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | arm64: dts: rockchip: Add Engicam PX30.Core SOMMichael Trimarchi2020-10-301-0/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. General features: - Rockchip PX30 - Up to 2GB DDR4 - eMMC 4 GB expandible - rest of PX30 features PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards. Possible baseboards are, - EDIMM2.2 - C.TOUCH 2.0 Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter KitJagan Teki2020-10-302-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out SOM's like PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | arm64: dts: rockchip: Add chosen node for ROCK-Pi N8Jagan Teki2020-10-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add chosen node in -u-boot.dtsi for ROCK-Pi N8 board. This will help to get serial out messages. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * | rockchip: dts: tinker: remove unnecessary nodeStefan Agner2020-10-301-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | The property reg-shift with the same value is present in the base device tree already. Remove unnecessary node from rk3288-tinker.dts. Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: dts: tinker: move i2c node to shared device treeStefan Agner2020-10-302-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C EEPROM is present on Tinker Board S as well. Move the i2c node to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree. Cc: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellWIP/29Oct2020Tom Rini2020-10-292-6/+25
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | - Armada 8k: Add NAND support via PXA3xx NAND driver (Baruch) - Armada 8k: Use ATF serdes init instead of the "old" U-Boot version (Baruch) - Minor update to Octeon TX/TX2 defconfig (Stefan)
| * | | arm: dts: armada-cp110-master: update nand-controllerBaruch Siach2020-10-291-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align node properties to kernel dts node. The change of compatible property does not affect any currently supported board. Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility with the current driver. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
| * | | arm: dts: armada-cp110-slave: add missing cps_nandShmuel Hazan2020-10-291-0/+16
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Align node properties to kernel dts node. Keep U-Boot specific nand-enable-arbiter, and num-cs for compatibility with the current driver. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Shmuel Hazan <shmuel.h@siklu.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* | | Merge tag 'xilinx-for-v2021.01-v2' of ↵Tom Rini2020-10-297-115/+150
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x
| * | | arm64: zynqmp: Fix zynqmp mini qspi max frequencyT Karthik Reddy2020-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For zynqmp qspi, frequencies up to 40MHz will work irrespective of feedback clock enabled or disabled. If we want higher than 40Mhz the feedback clock should be enabled. With spi-max-frequency 108MHz it is not working when the feedback clock is disabled. Change it to 40MHz so that it works irrespective of feedback clock enabled or disabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | arm64: versal: Update mini u-boot eMMC node parametersAshok Reddy Soma2020-10-272-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mini u-boot eMMC dt parameters are not in sync with full u-boot dt. Frequency for eMMC is fixed to 25Mhz. Due to this, mmc multi-block write commands are failing. Increase frequency to 200Mhz to fix this issue. Add bus-width = <8>, non-removable and disable-wp properties to the node as this is eMMC. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Add Z-turn board V5Alexandre GRIVEAUX2020-10-274-108/+137
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding Z-turn board V5 to resolve the change between: "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035 "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031 At this time the S25FL128SAGNFI003 doesn't work because of bug: *** Warning - spi_flash_probe_bus_cs() failed, using default environment zynq-zturn was checked on V5 board, same error. Maybe Z-turn board have the same problem (board with W25Q128BVFIG). Signed-off-by: Alexandre GRIVEAUX <agriveaux@deutnet.info> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-10-297-0/+394
|\ \ \ | |/ / |/| | | | | | | | | | | - Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support
| * | board: kontron: add sl28 supportMichael Walle2020-10-237-0/+394
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for the Kontron SMARC-sAL28 board. This includes just the bare minimum to be able to bring up the board and boot linux. For now, the Single and Dual PHY variant is supported. Other variants will fall back to the basic variant. In particular, there is no watchdog support for now. This means that you have to disable the default watchdog, otherwise you'll end up in the recovery bootloader. See the board README for details. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiWIP/22Oct2020Tom Rini2020-10-221-10/+33
|\ \ \ | |/ / |/| | | | | | | | - sun8i emac changes (Andre) - SCP firmware (Samuel)
| * | sunxi: binman: Add support for including SCP firmwareSamuel Holland2020-10-221-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner sun50i SoCs contain an OpenRISC 1000 CPU that functions as a System Control Processor, or SCP. ARM Trusted Firmware (ATF) communicates with the SCP over SCPI to implement the PSCI system suspend, shutdown and reset functionality. Currently, SCP firmware is optional; the system will boot and run without it, but system suspend will be unavailable. Since all communication with the SCP is mediated by ATF, the only thing U-Boot needs to do is load the firmware into SRAM. The SCP firmware occupies the last 16KiB of SRAM A2, immediately following ATF. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Update FIT component descriptionsSamuel Holland2020-10-221-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit d879616e9e64 ("spl: fit: simplify logic for FDT loading for non-OS boots"), the SPL looks at the "os" properties of FIT images to determine where to append the FDT. The "os" property of the "firmware" image also determines how to execute the next stage of the boot process, as in 1d3790905d9c ("spl: atf: introduce spl_invoke_atf and make bl31_entry private"). For this reason, the next stage must be specified in "firmware", not in "loadables". To support this additional functionality, and to properly model the boot process, where ATF runs before U-Boot, add the "os" properties and swap the firmware/loadable images in the FIT image. Since this description was copied as an example in commit 70248d6a2916 ("binman: Support generating FITs with multiple dtbs"), update those examples as well for correctness and consistency. Acked-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Use a macro for the BL31 load addressSamuel Holland2020-10-221-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This consolidates the SoC-specific part at the top of the file to avoid cluttering it up with preprocessor conditions. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Provide a default BL31 filenameSamuel Holland2020-10-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to commit 7f7f8aca8257 ("sunxi: Convert 64-bit boards to use binman"), if the BL31 environment variable was not defined, the firmware would be loaded from a file "bl31.bin" in the current directory. Restore that behavior by providing that as the default filename in case no entry arg is provided, which will be the case if the environment variable is unset. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: binman: Fix spacing between nodesSamuel Holland2020-10-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Nodes should have a blank line separating them from sibling nodes and properties. Add the necessary lines. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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