summaryrefslogtreecommitdiff
path: root/arch/arm/dts
Commit message (Collapse)AuthorAgeFilesLines
* rockchip: rk3128: add device tree fileKever Yang2017-11-303-0/+900
| | | | | | | | | | | | | | Add dts binding header for rk3128, files origin from kernel. Series-Changes: 2 - fix i2c address - add saradc and usb phy node - emmc using fifo mode for there is no dma support in rk3128 emmc - add some clock id in cru.h Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-shTom Rini2017-11-303-1/+16
|\
| * ARM: rmobile: Rework the ULCB CPLD driverMarek Vasut2017-11-301-0/+9
| | | | | | | | | | | | | | | | Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Migrate boards to RCar IIC driversMarek Vasut2017-11-301-0/+4
| | | | | | | | | | | | | | | | | | Stop using the old ad-hoc SH I2C driver and use the new RCar IIC driver instead. The SH I2C driver should be deprecated and removed eventually. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Use PRR driver on all Gen3 boardsMarek Vasut2017-11-302-0/+2
| | | | | | | | | | | | | | | | | | Mark the PRR as u-boot,dm-pre-reloc in all Gen3 board DTs as it is needed very early and turn on the CONFIG_SYSCON to allow the PRR driver to bind as a syscon uclass. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Fix eMMC signal voltage on ULCBMarek Vasut2017-11-301-1/+1
| | | | | | | | | | | | | | | | The eMMC is 1V8 device only and the signaling is always 1V8, fix the DT for ULCB to describe the hardware correctly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2017-11-301-1/+14
|\ \
| * | arm: mvebu: add nand pinsSean Nyekjaer2017-11-301-1/+14
| |/ | | | | | | | | Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
* | ARM: dts: Rename logicpd-toredp-37xx-devkit in U-BootAdam Ford2017-11-291-0/+2
| | | | | | | | | | | | | | | | | | | | In U-Boot, this device tree is compatible with both the Torpedo and SOM-LV kits. Let's rename it in the device tree since the U-Boot code and show a more generic OMAP3 name. The code auto detects between the two and loads the proper DTB file for Linux. This would eliminate the SOM-LV showing the name Torpedo during boot and hopefully eliminate some confusion. Signed-off-by: Adam Ford <aford173@gmail.com>
* | board: atmel: add sama5d2_ptc_ek boardLudovic Desroches2017-11-293-0/+236
| | | | | | | | | | | | | | | | Add the SAMA5D2 PTC EK board and remove the SAMA5D2 PTC ENGI board which was a prototype. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* | ARM: DTS: stm32: update rcc compatible for STM32F746Patrice Chotard2017-11-291-1/+1
| | | | | | | | | | | | | | | | | | Align the RCC compatible string with the one used by kernel. It will allow to use the same clock driver for STM32F4 and STM32F7 and to manage the differences between the 2 SoCs Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* | ARM: DTS: stm32: add pwrcfg node for stm32f746Patrice Chotard2017-11-292-0/+11
|/ | | | | | | | This node is needed to enable performance mode when system frequency is set up to 200Mhz. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* Merge tag 'xilinx-for-v2018.01' of git://www.denx.de/git/u-boot-microblazeTom Rini2017-11-2923-130/+910
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2018.1 Zynq: - Add support for Syzygy and cc108 boards - Add support for mini u-boot configurations (cse) - dts updates - config/defconfig updates in connection to Kconfig changes - Fix psu_init handling ZynqMP: - SPL fixes - Remove slcr.c - Fixing r5 startup sequence - Add support for external pmufw - Add support for new ZynqMP chips - dts updates - Add support for zcu102 rev1.0 board Drivers: - nand: Support external timing setting and board init - ahci: Fix wording - axi_emac: Wait for bit, non processor mode, readl/write conversion - zynq_gem: Fix SGMII/PCS support
| * arm64: zynqmp: Enable watchdog by defaultShubhrajyoti Datta2017-11-281-0/+4
| | | | | | | | | | | | | | Enable watchdog in dts for zcu102. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add note about si5328 interruptMichal Simek2017-11-281-0/+5
| | | | | | | | | | | | Add comment about irq present on the board connected to PL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: usb: Correct IOMMU node for making SMMU work with USBAnurag Kumar Vulisha2017-11-281-4/+4
| | | | | | | | | | | | | | | | This patch makes SMMU work by moving the iommus node under the dwc3 child entry from parent node. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Remove clock setting from dtsiMichal Simek2017-11-281-2/+0
| | | | | | | | | | | | clock setting is handled via clk dtsi file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Uncomment snps,quirk-frame-length-adjustment flag in dwc3Anurag Kumar Vulisha2017-11-281-2/+2
| | | | | | | | | | | | | | This patch uncomments snps,quirk-frame-length-adjustment which has the value to adjust the SOF/ITP generated from the controller. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add USB OTG interrupts support in dtManish Narani2017-11-281-2/+2
| | | | | | | | | | | | | | | | | | This patch adds OTG interrupt support in device tree. It will add an extra interrupt line number dedicated to OTG events. This will enable OTG interrupts to serve in DWC3 OTG driver. Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Enabled CCI support for USBManish Narani2017-11-281-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds CCI support for USB when CCI is enabled in design. This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg' property is added in order to modify a register in that to enable coherency in Hardware. Also add address to unit name to avoid dtc warning Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add support reading SoC revision using nvmem driver in dwc3Anurag Kumar Vulisha2017-11-281-0/+4
| | | | | | | | | | | | | | | | This patch adds support for reading silicon revision using zynqmp nvmem driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Move nodes which have no reg property out of busMichal Simek2017-11-283-50/+50
| | | | | | | | | | | | | | Nodes without reg properties shouldn't be placed in amba node. Move them out. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: dt: Add AMS nodeMichal Simek2017-11-282-0/+38
| | | | | | | | | | | | | | | | | | The AMS includes an ADC as well as on-chip sensors that can be used to sample external voltages and monitor on-die operating conditions, such as temperature and supply voltage levels. Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 siliconManish Narani2017-11-281-0/+4
| | | | | | | | | | | | | | | | | | This patch sets host quirk2 bit field for No 1.8V supported in case of 1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This property will ensure the SD runs on High Speed mode. Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Use reset controller framework for asserting/de-asserting resetAnurag Kumar Vulisha2017-11-281-2/+1
| | | | | | | | | | | | | | | | | | | | This patch modifies the phy_zynqmp.c driver to use reset-controller framework for asserting/de-asserting reset for High Speed modules. Also fix documentation and dtsi. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add reset-controller support in serdes driverAnurag Kumar Vulisha2017-11-281-0/+13
| | | | | | | | | | | | | | | | This patch add the reset nodes in zynqmp.dtsi which are used by reset-controller framework Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Remove tx_termination_fix detection on silicon v1Michal Simek2017-11-281-1/+2
| | | | | | | | | | | | | | | | Only silicon v1 requires this termination fix. With new nvmem soc revision nvmem detection driver this can be autodetected at run time and this flag is not needed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add support for zynqmp nvmem firmware driverNava kishore Manne2017-11-281-0/+10
| | | | | | | | | | | | | | Add support for zynqmp nvmem firmware driver. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add support for zcu102 1.0 revMichal Simek2017-11-283-1/+39
| | | | | | | | | | | | 1.0 rev is the latest rev. Describe information in eeprom. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Update device tree for pinmuxMichal Simek2017-11-282-0/+295
| | | | | | | | | | | | | | Added pin control support in device tree for zynqmp. Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Remove local-mac-address from dtsi fileMichal Simek2017-11-285-8/+0
| | | | | | | | | | | | | | | | Generic dtsi file can't use the same mac address for all. U-Boot read mac from eeprom in zcu102 case and for others random mac address is generated. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Use SPDX license with dc4Michal Simek2017-11-281-4/+1
| | | | | | | | | | | | Just header change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Remove leading 0s from mtd table for spi flashesMichal Simek2017-11-282-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dtc reports issues with it. arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning (unit_address_format): Node /amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning (unit_address_format): Node /amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (unit_address_format): Node /amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should not have leading 0s arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning (unit_address_format): Node /amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should not have leading 0s Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add missing alias for gem0 for ep108Michal Simek2017-11-281-0/+1
| | | | | | | | | | | | Add missing alias for gem0 for ep108 to have proper sequence number. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: zcu102: Modifying GTR lane-0 to PCIeBharat Kumar Gogada2017-11-281-2/+2
| | | | | | | | | | | | | | | | - Enabling GTR lane-0 to PCIe - Enabling PCIe node in device tree Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Update device tree for gpioChirag Parekh2017-11-281-1/+1
| | | | | | | | | | | | | | Used defines rather than raw values for gpio configurations. Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add revB string to compatible stringMichal Simek2017-11-281-0/+1
| | | | | | | | | | | | | | Some user space libraries reading platform compatible string and based on that changing behavior. Mark revB board with revB string. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Use revision in dts file descriptionMichal Simek2017-11-281-1/+1
| | | | | | | | | | | | Trivial change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: PM: Specify power domains for DP related nodesJyotheeswar Reddy Mutthareddyvari2017-11-281-1/+3
| | | | | | | | | | | | | | | | | | | | Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is causing genpd to trigger a power down request for DP domain, making all DP related peripherals unusable. So assign power domains for all DP related nodes to enable proper accounting of DP power domain usage. Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: disable smmuNaga Sureshkumar Relli2017-11-281-26/+1
| | | | | | | | | | | | | | This patch disables the smmu and also removes the mmu-masters Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: rtc: Add calibrationNava kishore Manne2017-11-281-0/+1
| | | | | | | | | | | | | | | | This patch adds the calibration property with required value, calculated based on rtc input crystal oscillator frequency (32.768Khz). Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add SMMU support for SATA IPAnurag Kumar Vulisha2017-11-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AXI master interface in CEVA AHCI controller requires two unique Write/Read ID tags per port. This is because, ahci controller uses different AXI ID[3:0] bits for identifying non-data transfers(like reading descriptors, updating PRD tables, etc) and data transfers (like sending/receiving FIS).To make SMMU work with SATA we need to add correct SMMU stream id for SATA. SMMU stream id for SATA is determined based on the AXI ID[1:0] as shown below SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0] Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so SMMU ID = 001, 0011, 00, 00, AXI ID[1:0] Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1 as said above) we get four different SMMU stream id's combinations for SATA. These AXI ID can be configured using PAXIC register. In this patch we assumed the below AXI ID values Read ID/ Write ID for Non-Data Port0 transfers = 0 Read ID/ Write ID for Data Port0 transfers = 1 Read ID/ Write ID for Non-Data Port1 transfers = 2 Read ID/ Write ID for Data Port1 transfers = 3 Based on the above values,SMMU stream ID's for SATA will be 0x4c0 & 0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be added to iommus dts property. This patch does the same. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: dts: xilinx: fix PCI bus dtc warningsRob Herring2017-11-281-0/+1
| | | | | | | | | | | | | | | | | | dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add missing gpio property to dtsiMichal Simek2017-11-281-0/+1
| | | | | | | | | | | | | | | | All gpio controllers should contain this property. This property is not checked by the code that's why this issue wasn't found earlier. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Update the GPU address sizeHyun Kwon2017-11-281-1/+1
| | | | | | | | | | | | | | | | The correct register size is 0x10000, otherwise it overlaps with other register space. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Add clock name for GPUMadhurkiran Harikrishnan2017-11-281-0/+1
| | | | | | | | | | | | | | | | This patch will add names to the clocks used by GPU. Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Label whole PL part as fpga_full regionNava kishore Manne2017-11-281-1/+8
| | | | | | | | | | | | | | This will simplify dt overlay structure for the whole PL. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Fix broken architected timer interrupt triggerMichal Simek2017-11-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extract from Linux mainline patch: The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: PM: Add IRQSoren Brinkmann2017-11-281-0/+2
| | | | | | | | | | | | | | | | PM callbacks are delivered to the NS OS. Let the PM driver handle the IRQ and retrieve callback data from the secure HW. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Reduced min-residency time for idle state nodeJolly Shah2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0. Tried lower values 5ms and 8ms and it worked fine with Debug Off. But to accommodate PM Debug On case, 10 ms is required. With this change, low power idle state is into effect more frequently. Measured boot time with PM debugs On and Off. No change observed compared to 100ms value. Signed-off-by: Jolly Shah <jollys@xilinx.com> Acked-by: Will Wong <willw@xilinx.com> Tested-by: Koteswararao Nayudu <kotin@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
View Lorry Controller Status