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* Layerscape: Add crypto node in device treeGaurav Jain2022-04-121-0/+39
| | | | | | | LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* spi: fsl_dspi: rename num-cs to spi-num-chipselectsMichael Walle2021-11-091-1/+1
| | | | | | | | | The official devicetree bindings specifies spi-num-chipselects as the name. Use it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* Revert "arm64: Layerscape: Survive LPI one-way reset workaround"Tom Rini2021-10-301-6/+0
| | | | | | | | | | | | | | Ad-hoc bindings that are not part of the upstream device tree / bindings are not allowed in-tree. Only bindings that are in-progress with upstream and then re-synced once agreed upon are. This reverts commit af288cb291da3abef6be0875527729296f7de7a0. Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Reported-by: Michael Walle <michael@walle.cc> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marc Zyngier <maz@kernel.org>
* arm64: dts: ls208xa: add gpio nodeBiwen Li2021-02-081-1/+45
| | | | | | | Add gpio node for SoC LS208xA Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: dts: ls2080a: add label to pcie nodes in dtsWasim Khan2020-12-101-5/+6
| | | | | | | | Add label to pcie nodes in dts so that these nodes are easy to refer. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm64: Layerscape: Survive LPI one-way reset workaroundHou Zhiqiang2020-09-241-0/+6
| | | | | | | | | | | The workaround of LPI one-way reset issue is broken by the series: https://patchwork.ozlabs.org/project/uboot/list/?series=192398 This patch is to add DT node for GIC RD tables and create corresponding reserved-memory node in kernel DT to fix it. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* treewide: Update fsl qspi node dt properties as per spi-mem driverKuldeep Singh2020-05-191-2/+2
| | | | | | | | | | | | | | According to new qspi driver, some properties like "bus-num, num-cs, big-endian" are no longer used. Device endiannes can be determined from device-type data in driver. Now use board specific compatibles, generic node names and specific labels to align with linux device-tree properties. Also consolidate spi-max-frequency to 50Mhz treewide. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: dts: ls2088ardb: add DPMAC and PHY nodesIoana Ciornei2020-04-291-6/+69
| | | | | | | | | | | | | In order to maintain compatibility with the Linux DTS, the entire fsl-mc node is added but instead of being probed by a dedicated bus driver it will be a simple-mfd. Also, annotate the external MDIO nodes and describe the PHYs (4 x AQR405 and 4 x CS4340). Also, add phy-handles for the dpmacs to their associated PHY. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: dts: ls2088a: add external MDIO nodesIoana Ciornei2020-04-291-0/+15
| | | | | | | | Add the External MDIO1 device node found in the WRIOP global memory region. This is needed for management of external PHYs. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: dts: fsl-ls2088a: add i2c node supportchuanhua han2019-08-221-0/+36
| | | | | | | | One ls2088a, there are four I2C controllers. So add I2C nodes in dts for ls2088a. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* armv8: dts: fsl-ls2080a: add sata node supportPeng Ma2018-12-061-0/+8
| | | | | | | | | | | | | One ls2080a, there is one SATA 3.0 advanced host controller interface which is a high-performance SATA solution that delivers comprehensive and fully-compliant generation 3 (1.5 Gb/s - 6.0 Gb/s) serial ATA capabilities, in accordance with the serial ATA revision 3.0 of Serial ATA International Organization. Add sata node to support this feature. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2088a: add eSDHC nodeYinbo Zhu2018-09-271-0/+8
| | | | | | | This patch is to add eSDHC node for ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SPDX: Convert all of our multiple license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: dts: Freescale: re-license device tree files under GPLv2+/X11Pankaj Bansal2018-01-231-1/+1
| | | | | | | | | | | | | | | | | The current GPL only licensing on the device trees makes it very impractical for other software components licensed under another license. To make it easier to reuse them, re-license the the device trees for Freescale (now NXP) SoCs and boards under GPLv2+/X11 dual license. Same trend is followed in linux. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: add PCIe dts nodeMinghuan Lian2017-01-181-0/+60
| | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: Add USB node in dts for ls2080aSriram Dash2016-10-071-0/+14
| | | | | | | | Add the USB node for LS2080a in dts. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> [York Sun: replace ls2080 with ls2080a in commit message] Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIsAbhimanyu Saini2016-06-281-61/+0
| | | | | | | | | | | | Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* dts: ls2080aqds: Add QSPI dts nodeYuan Yao2016-06-101-0/+10
| | | | | | | Add QSPI controller and slave dts node for LS2080AQDS board. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: LS2080A: Rename LS2085A to reflect LS2080APrabhakar Kushwaha2015-11-301-0/+129
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc. So renaming existing LS2085A code base to reflect LS2080A (Prime personality) Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>