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* sunxi: psci: Fix sunxi_power_switch on sun8i-r40 platformqianfan Zhao2022-06-261-1/+1
| | | | | | | | | | | | | | | linux system will die if we offline one of the cpu on R40 based board: eg: echo 0 > /sys/devices/system/cpu/cpu3/online The reason is that the R40 version of sunxi_cpu_set_power always passes 0 for the CPU number, so we turn off CPU0, regardless of what CPU the CPU_OFF request came for. Fix this by passing the proper CPU number, as there are proper power clamp registers for every of the four cores. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* armv8: always use current exception level for TCR_ELx accessAndre Przywara2022-06-163-7/+27
| | | | | | | | | | | | | | | | | | | | | | Currently get_tcr() takes an "el" parameter, to select the proper version of the TCR_ELx system register. This is problematic in case of the Apple M1, since it runs with HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the TCR_EL1 layout, and we get the wrong version. For U-Boot's purposes the only sensible choice here is the current exception level, and indeed most callers treat it like that, so let's remove that parameter and read the current EL inside the function. This allows us to check for the E2H bit, and pretend it's EL1 in this case. There are two callers which don't care about the EL, and they pass 0, which looks wrong, but is irrelevant in these two cases, since we don't use the return value there. So the change cannot affect those two. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Tested-by: Mark Kettenis <kettenis@openbsd.org>
* caam: Fix crash in case caam_jr_probe failedYe Li2022-05-202-2/+2
| | | | | | | | | If probing caam_jr returns failure, the variable "dev" will not be initialized, so we can't use dev->name for the error print. Otherwise it will cause crash. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
* armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUsStephen Carlson2022-04-261-3/+7
| | | | | | | | | | | NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: fix the function mismatch issueYuantian Tang2022-04-261-2/+2
| | | | | | Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig optionMichael Walle2022-04-262-11/+21
| | | | | | | | | | | | | | | | | | There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: psci: skip setup code if we are not EL3Michael Walle2022-04-261-0/+3
| | | | | | | | If we are running in EL2 skip PSCI implementation setup. This avoids an exception if CONFIG_ARMV8_PSCI is set, but u-boot is started by TF-A. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: get rid of smc_call()Michael Walle2022-04-264-49/+31
| | | | | | | | | | | | | | | | | | | | There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle <michael@walle.cc> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: include psci_update_dt() unconditionallyMichael Walle2022-04-261-4/+5
| | | | | | | | | | | | | | psci_update_dt() is also required if CONFIG_ARMV8_PSCI is set, that is, if u-boot is the PSCI provider. Guard the check which is intended to call into the PSCI implementation in the secure firmware, by the proper macro SEC_FIRMWARE_ARMV8_PSCI. Mark the function as weak because - unfortunately - there is already a stub of the same function in arch/arm/mach-rmobile/psci-r8a779a0.c which does not the same as the common one. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: layerscape: Disable erratum A009007 on LS1021A, LS1043A, and LS1046ASean Anderson2022-04-262-3/+0
| | | | | | | | | | | | | | | | | | | | | | | This erratum is reported to cause problems on these processors [1-3]. The problem is usually with the clocking, which is supposed to be configured by the RCW [4]. However, if it is not set, or if the default clocking is not correct, then this erratum will cause an SError. However, according to Ran Wang in [1]: " ... this erratum is used to pass USB compliance test only, you could disable this workaround on your board if you don't any USB issue on normal use case, I think it's fine." So just disable this erratum by default for these processors. [1] https://lore.kernel.org/all/761ddd61-05c1-d9b8-ac90-b8f425afde6c@denx.de/ [2] https://community.nxp.com/t5/Layerscape/LS1046A-U-BOOT-HALT-AT-ERRATUM-A0090078/m-p/742993 [3] https://community.nxp.com/t5/QorIQ/Why-does-the-LS1043A-U-Boot-hang-at-code-that-fixes-erratum/m-p/644412 [4] https://source.codeaurora.org/external/qoriq/qoriq-components/rcw/tree/ls1046ardb/usb_phy_freq.rcw Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Ran Wang <ran.wang_1@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: fsl-layerscape: Respect Kconfig for erratum A009007Sean Anderson2022-04-251-0/+3
| | | | | | | | There is a Kconfig for this erratum, but it is ignored for armv8. Respect it. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm: set cntfrq_el0 if CONFIG_COUNTER_FREQUENCY is validPeng Fan2022-04-215-7/+7
| | | | | | | | Since COUNTER_FREQUENCY is obselete, so set cntfrq_el0 if CONFIG_COUNTER_FREQUENCY is valid Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
* include/configs: drop COUNTER_FREQUENCYPeng Fan2022-04-211-1/+1
| | | | | | Since we have CONFIG_COUNTER_FREQUENCY enabled, no need COUNTER_FREQUENCY Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2022-04-211-3/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | - mrvl_uart.sh: Remove script (Pali) - Fix Espressobin build for configs where ENV is not in SPI (Rogier) - mvebu: a37xx: Add support for reading OTP (Pali) - mvebu: uDPU: Ethernet fixes and misc DT and defconfig changes (Robert) - mvebu: Add support for reading LD0 and LD1 eFuse (Pali) - kwboot: Replace fstat()+st_size by lseek()+SEEK_END (Pali) - mvebu: turris_omnia: Enable CONFIG_CMD_FUSE (Pali) - arm: Add CONFIG_SPL_SYS_NO_VECTOR_TABLE used on 32bit MVEBU (Pali) - mvebu: a37xx: Add support for writing Security OTP values (Pali) - mvebu: turris: Misc enhancements and cleanups / fixes (Pali) - Sheevaplug : Use Marvell uclass mvgbe and PHY driver for Ethernet (Tony)
| * arm: Introduce new CONFIG_SPL_SYS_NO_VECTOR_TABLE optionPali Rohár2022-04-211-3/+1
| | | | | | | | | | | | | | Move OMAP4 specific option for disabling overwriting vector table into config option CONFIG_SPL_SYS_NO_VECTOR_TABLE. Signed-off-by: Pali Rohár <pali@kernel.org>
* | armv8: layerscape: env: Switch to arch_env_get_location()Marek Vasut2022-04-211-1/+1
|/ | | | | | | | | | | | | | | | | | Implement arch_env_get_location() instead of env_get_location(), so that the env_get_location() can be implemented on board level and override the arch_env_get_location() architecture defaults. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Adam Ford <aford173@gmail.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Vladimir Oltean <vladimir.oltean@nxp.com>
* Layerscape: Enable Job ring driver model.Gaurav Jain2022-04-122-1/+28
| | | | | | | | | | | | | LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162 platforms are enabled with JR driver model. removed sec_init() call from board files. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Michael Walle <michael@walle.cc>
* arm: Remove unused ep93xx codeTom Rini2022-04-087-812/+0
| | | | | | | There are no platforms for this architecture anymore, remove unused code. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: fsl-layerscape: Migrate more DP-DDR options to KconfigTom Rini2022-04-081-0/+25
| | | | | | | | | Based on current usage, migrate a number of DP-DDR related options to Kconfig. Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* arm64: ls1046a: Support semihosting fallbackSean Anderson2022-04-011-1/+2
| | | | | | | | Use the semihosting_enabled function to determine whether or not to enable semihosting devices. This allows for graceful fallback in the event a debugger is not attached. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm64: Save spsr in pt_regsSean Anderson2022-04-011-1/+4
| | | | | | | | This register holds "pstate" which includes (among other things) the instruction mode the CPU was in when the exception was taken. This is necessary to correctly interpret instructions at elr. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm64: Save esr in pt_regsSean Anderson2022-04-011-2/+4
| | | | | | | | | To avoid passing around an extra register everywhere, save esr in pt_regs like the rest. For proper alignment we need to have a second (unused) register. All the printfs have to be adjusted, since it's now an unsigned long and not an int. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* ls1046ardb: Add support for JTAG bootSean Anderson2022-04-011-0/+2
| | | | | | | | | | | | | | | This adds support for booting entirely from JTAG while using a hard-coded RCW. With these steps, it is not necessary to program a "good" RCW using CodeWarrior. The method here can be performed with any JTAG adapter supported by OpenOCD, including the on-board CMSIS-DAP (albeit very slowly). These steps require LS1046A support in OpenOCD, which was added in [1]. [1] https://sourceforge.net/p/openocd/code/ci/5b70c1f679755677c925b4e6dd2c3d8be4715717/ Signed-off-by: Sean Anderson <sean.anderson@seco.com> [trini: Add reference to doc/board/nxp/ls1046ardb.rst]
* video: fsl: colibri_vf: Drop FSL DCU driverSimon Glass2022-03-281-4/+0
| | | | | | | | | This does not use driver model and is more than two years past the migration date. Drop it. It can be added back later if needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_ARMV8_SWITCH_TO_EL1 to KconfigTom Rini2022-03-181-0/+6
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_ARMV8_SWITCH_TO_EL1 Cc: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
* Convert CONFIG_ARMV7_SECURE_BASE et al to KconfigTom Rini2022-03-181-0/+31
| | | | | | | | | This converts the following to Kconfig: CONFIG_ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_MAX_SIZE CONFIG_ARMV7_SECURE_RESERVE_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'v2022.04-rc4' into nextTom Rini2022-03-141-2/+2
|\ | | | | | | Prepare v2022.04-rc4
| * sunxi: f1c100s: Fix FEL registers restoreAndre Przywara2022-03-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 88998f777531 ("arm: arm926ej-s: Add sunxi code") introduced the ARM926 version of the code to save and restore some FEL state, to be able to return to the BROM FEL code after the SPL has run. However during review a change was made, that happened to mess up the register restore part, so SCTLR and CPSR ended up with the wrong values, breaking return to FEL. Use the same offset that we actually save those registers to, to make FEL booting actually work on the Lichee Pi Nano. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | Convert CONFIG_CHIP_SELECTS_PER_CTRL to KconfigTom Rini2022-03-033-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_CHIP_SELECTS_PER_CTRL Cc: Alison Wang <alison.wang@nxp.com> Cc: Pramod Kumar <pramod.kumar_1@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | armv8: Fix and simplify branch_if_master/branch_if_slaveAndre Przywara2022-03-022-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The branch_if_master macro jumps to a label if the CPU is the "master" core, which we define as having all affinity levels set to 0. To check for this condition, we need to mask off some bits from the MPIDR register, then compare the remaining register value against zero. The implementation of this was slighly broken (it preserved the upper RES0 bits), overly complicated and hard to understand, especially since it lacked comments. The same was true for the very similar branch_if_slave macro. Use a much shorter assembly sequence for those checks, use the same masking for both macros (just negate the final branch), and put some comments on them, to make it clear what the code does. This allows to drop the second temporary register for branch_if_master, so we adjust all call sites as well. Also use the opportunity to remove a misleading comment: the macro works fine on SoCs with multiple clusters. Judging by the commit message, the original problem with the Juno SoC stems from the fact that the master CPU *can* be configured to be from cluster 1, so the assumption that the master CPU has all affinity values set to 0 does not hold there. But this is already mentioned above in a comment, so remove the extra comment. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | armv8: Force SP_ELx stack pointer usageAndre Przywara2022-03-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In ARMv8 we have the choice between two stack pointers to use: SP_EL0 or SP_ELx, which is banked per exception level. This choice is stored in the SP field of PState, and can be read and set via the SPSel special register. When the CPU takes an exception, it automatically switches to the SP_ELx stack pointer. Trusted Firmware enters U-Boot typically with SPSel set to 1, so we use SP_ELx all along as our sole stack pointer, both for normal operation and for exceptions. But if we now for some reason enter U-Boot with SPSel cleared, we will setup and use SP_EL0, which is fine, but leaves SP_ELx uninitialised. When we now take an exception, we try to save the GPRs to some undefined location, which will usually end badly. To make sure we always have SP_ELx pointing to some memory, set SPSel to 1 in the early boot code, to ensure safe operation at all times. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | armv8: Always unmask SErrorsAndre Przywara2022-03-022-9/+3
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv8 architecture describes the "SError interrupt" as the fourth kind of exception, next to synchronous exceptions, IRQs, and FIQs. Those SErrors signal exceptional conditions from which the system might not easily recover, and are normally generated by the interconnect as a response to some bus error. A typical situation is access to a non-existing memory address or device, but it might be deliberately triggered by a device as well. The SError interrupt replaces the Armv7 asynchronous abort. Trusted Firmware enters U-Boot (BL33) typically with SErrors masked, and we never enable them. However any SError condition still triggers the SError interrupt, and this condition stays pending, it just won't be handled. If now later on the Linux kernel unmasks the "A" bit in PState, it will immediately take the exception, leading to a kernel crash. This leaves many people scratching their head about the reason for this, and leads to long debug sessions, possibly looking at the wrong places (the kernel, but not U-Boot). To avoid the situation, just unmask SErrors early in the ARMv8 boot process, so that the U-Boot exception handlers reports them in a timely manner. As SErrors are typically asynchronous, the register dump does not need to point at the actual culprit, but it should happen very shortly after the condition. For those exceptions to be taken, we also need to route them to EL2, if U-Boot is running in this exception level. This removes the respective code snippet from the Freescale lowlevel routine, as this is now handled in generic ARMv8 code. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* spl: Provide more space to be used for storing SPL on imx28 OCRAMLukasz Majewski2022-02-052-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | With the current configuration provided in mxsimage{-spl}.mx28.cfg the size of SPL binary has been constrained to 32 KiB, due to "LOAD IVT" command with 0x8000 offset. The problem was that, the imx28 ROM takes the u-boot.sb and then extracts from it the IVT header and places it on the 0x8000 OCRAM offset overwriting any valid (i.e. loaded from eMMC or SPI-NOR) SPL code. This bug was unnoticed as the overwrite size was just 32 bytes, so the probability that some important code is altered was low. However, in the XEA board (where the SPL size is ~39KiB), the overwritten data was `(struct dm_spi_ops *) 0x800c <mxs_spi_ops>`, which is used during the boot process. As a result the SPL execution code hanged with "undefined instruction" abort as callbacks (with wrong addresses) from it were called. The fix is to change the OCRAM's offset where IVT is loaded to 0xE000, so the SPL can grow up to ~57KiB (the maximal size of OCRAM memory available is 0xE3FC). Signed-off-by: Lukasz Majewski <lukma@denx.de>
* mxs: power: Change sequence of enabling DCDC switchesLukasz Majewski2022-02-051-2/+2
| | | | | | | | | | | | | | The imx28 uses following voltage supplies hierarchy: VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM \-----> VDDD One shall first enable DCDC on the parent source (VDDIO) and then follow with its children. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2022-02-0314-161/+184
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the promised second part of the sunxi PR for 2022.04, albeit technially outside of the merge window. We were working on this full steam since the beginning of the year, and it deserves to be merged, I think. The main attraction is support for the F1C100s SoC, which sports a venerable ARM926 core. Support for this SoC and the LicheePi Nano board has been in Linux for years, and U-Boot patches were posted mid last year already. The new SoC using ARMv5 also means that the bulk of the new code should not touch any existing boards, although we did some refactorings first, of course, which actually cleans up some existing sunxi code. Compile tested for all 160 sunxi boards, and briefly tested on BananaPi M1, OrangePi Zero, Pine64 and Pine-H64. Tested by others on their boards, including F1C100s and F1C200s devices.
| * arm: arm926ej-s: Add sunxi codeIcenowy Zheng2022-02-046-0/+106
| | | | | | | | | | | | | | | | | | | | | | Some Allwinner SoCs use ARM926EJ-S core. Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * mach-sunxi: Move timer code to mach folderJesse Taube2022-02-042-117/+0
| | | | | | | | | | | | | | | | Both armv7 and arm926ejs use this timer code so move it to mach-sunxi. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * arm: arm926ej-s: start.S: port save_boot_params support from armv7 codeIcenowy Zheng2022-02-041-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | The ARMv7 start code has support for saving some boot params at the entry point, which is used by some SoCs to return to BROM. Port this to ARM926EJ-S start code. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * armv8: remove no longer needed lowlevel_init.SAndre Przywara2022-02-042-44/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we added Allwinner SoC support to ARMv8, we needed to pull in an implementation of lowlevel_init() calling the C function s_init(), as sunxi required it as this time. The last few patches got rid of this bogus requirement, and as sunxi was still the only user, we can now remove this lowlevel_init.S from ARMv8 altogether. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * sunxi: move early "SRAM setup" into separate fileAndre Przywara2022-02-042-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied from the original BSP U-Boot. The comment speaks of this being required before DRAM access gets enabled, but there is no indication that this would actually be required that early. Move this out of s_init(), into board_init_f(). Since this actually only affects a very few older SoCs, the actual code goes into the cpu/armv7 directory, to move it out of the way for all other SoCs. This also uses the opportunity to convert some #ifdefs over to the fancy IS_ENABLED() macros used in actual C code. We keep the s_init() stub around for now, since armv8's lowlevel_init still relies on it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * sunxi: move Cortex SMPEN setting into start.SAndre Przywara2022-02-042-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to their TRMs, Cortex ARMv7 CPUs with SMP support require the ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB maintenance operations are done. As we do those things still in start.S, we need to move the SMPEN bit setting there, too. This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR very early in start.S, and moves sunxi boards over to use that instead of the custom code we had in our board.c file (where it was called technically too late). In practice we got away with this so far, because at this point all the other cores were still in reset, so any broadcasting would have been ignored anyway. But it is architecturally cleaner to do it early, and we move a core specific piece of code out of board.c. This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few years back, and moves the respective logic into the new Kconfig entry. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | armv8: start.S: remove CONFIG_SYS_RESET_SCTRL codeAndre Przywara2022-02-031-37/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is some code that tries to "reset" the SCTLR_ELx register early in the boot process. The idea seems to be to guarantee some sane settings that U-Boot actually relies on, for instance running in little-endian mode, with the MMU off initially. However the current code has multiple problems: - For a start, no platform or config defines the symbol that would enable that code. - The code itself really only works if the bits that it tries to clear are already cleared: - If we run in big-endian mode initially, any previous loads would have been wrong already. That applies to the (optional) relocation code, but more prominently to the mask that it uses to clear those bits: "ldr x1, =0xfdfffffa" looks innocent, but actually involves a memory access to the literal pool, using the current endianness. - If we run with the MMU enabled, we are probably doomed already. We *could* hope that we are running with an identity mapping, but would need to do some cache maintenance to avoid losing dirty cache lines. - The idea of doing a read-modify-write of SCTLR is somewhat questionable to begin with, because as the owner of the current exception level we should initialise all bits of this register with a certain fixed value. - The code is unnecessarily complicated, and the function name is misspelled. While those problems *could* admittedly be fixed, the point that is does not seem to be used at all at the moment tells me we should just remove this code, and be it to not give a bad example. If people care, I could introduce some proper SCTLR initialisation code. We are about to work this out for the boot-wrapper[1] as we speak, but apparently we got away without doing this in U-Boot ever since, so it might not be worth the potential trouble. [1] https://lore.kernel.org/linux-arm-kernel/20220114105653.3003399-7-mark.rutland@arm.com/ Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | armv8: spl: Fix build with LINUX_KERNEL_IMAGE_HEADERAlper Nebi Yasak2022-02-031-0/+4
|/ | | | | | | | | | Setting LINUX_KERNEL_IMAGE_HEADER=y attempts to include an ARM64 Linux kernel image header at the start of both U-Boot proper and SPL binaries. However, some definitions that the image header uses are not included by the SPL linker script, resulting in a build error. Include them the way they are included in U-Boot proper's linker script to fix the error. Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
* Convert CONFIG_TIMESTAMP to KconfigSimon Glass2022-01-211-0/+1
| | | | | | | This converts the following to Kconfig: CONFIG_TIMESTAMP Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2022-01-202-11/+3
|\ | | | | | | | | | | | | | | | | | | - fdt_support: Add fdt_for_each_node_by_compatible() helper macro (Marek) - turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob (Pali) - pci_mvebu: Add support for Kirkwood PCIe controllers (Pali) - SPL: More verifications for kwbimage in SPL (Pali) - mvebu: Remove comphy_update_map() (Pali) - Minor misc stuff
| * fdt_support: Add fdt_for_each_node_by_compatible() helper macroMarek Behún2022-01-202-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add macro fdt_for_each_node_by_compatible() to allow iterating over fdt nodes by compatible string. Convert various usages of off = fdt_node_offset_by_compatible(fdt, start, compat); while (off > 0) { code(); off = fdt_node_offset_by_compatible(fdt, off, compat); } and similar, to fdt_for_each_node_by_compatible(off, fdt, start, compat) code(); Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | doc: replace @return by Return:Heinrich Schuchardt2022-01-191-1/+1
|/ | | | | | | | | | | | Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* common: spl: move armv7m-specific code to spl_perform_fixups()Ovidiu Panait2022-01-181-0/+6
| | | | | | | | Factor out armv7m fragment to spl_perform_fixups(), which is an arch/board specific function designed for this purpose. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
* armv8: apple: Disable PSCI resetMark Kettenis2022-01-141-1/+1
| | | | | | | | Apple's ARMv8 cores don't implement EL3 and therefore don't provide a PSCI implementation. So don't attempt to use PSCI to reset on machines using Apple SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
* arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c: Fix spelling of ↵Vagrant Cascadian2022-01-131-1/+1
| | | | "resetting".
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