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| * bootstd: Create a new BOOTMETH_DISTROSimon Glass2023-05-131-1/+9
| | | | | | | | | | | | | | | | | | | | We cannot be sure what bootmeth a distro will need to use. Add a new BOOTMETH_DISTRO option which collects these together. Select this from BOOTSTD_DEFAULTS so that it is clear what is needed. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Make BOOTMETH_EFILOADER depend on EFI_LOADER, select if EFI_LOADER] Signed-off-by: Tom Rini <trini@konsulko.com>
| * bootstd: Rename distro and syslinux to extlinuxSimon Glass2023-05-1318-126/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the terms 'distro' to mean extlinux but they are not really the same. 'Distro' could refer to any method of booting a distribution, whereas extlinux is a particular method. Also we sometimes use syslinux, but it is better to use the same term in all cases. Rename distro to syslinux and also update bootstd uses of syslinux to use extlinux instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| * bootstd: Tidy up reporting of errorsSimon Glass2023-05-134-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | In a few cases the error handling is not quite right. Make sure we return the actual error in distro_efi_read_bootflow_file() rather than -EINVAL. Return -IO when a file cannot be read. Also show the error name if available. This does not change operation, but does make it easier to diagnose problems. Signed-off-by: Simon Glass <sjg@chromium.org>
| * bootstd: Correct default boot commandSimon Glass2023-05-133-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch to relax flag requirements was not accepted[1], so we still have to have separate bootcommands depending on CMD_BOOTFLOW_FULL. The previous attempt at this did not work, since it used the wrong name for the options. Fix this and change the message to mention BOOTSTD_FULL since this affects not just the flags, but all functionality, so is more likely what the user wants. Drop the useless condition on CMD_BOOTFLOW_FULL while we are here. [1] https://patchwork.ozlabs.org/project/uboot/patch/20230329071655.1959513-2-sjg@chromium.org/ Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: a91492b6e9c ("bootstd: Provide a default command")
| * bootstd: Require HUSH_PARSER for script bootingSimon Glass2023-05-131-0/+1
| | | | | | | | | | | | | | | | Armbian uses a script which needs the HUSH parser. It is likely that other distros will do the same. Enable it by default, just in case. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Jonas Karlman <jonas@kwiboo.se>
| * bootstd: usb: Avoid initing USB twiceSimon Glass2023-05-132-0/+8
| | | | | | | | | | | | | | | | | | | | | | This causes crashes on some boards, e.g. rockpro64. In any case, we should not do it. Check the usb_started flag to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Tom Rini <trini@konsulko.com>
| * usb: Tidy up the usb_start flagSimon Glass2023-05-136-8/+6
| | | | | | | | | | | | | | | | | | | | | | This should be declared in a header file so that type-checking works correctly. Add a single declaration to usb.h and remove the others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * bootstd: Work around missing partition 1Simon Glass2023-05-131-1/+8
|/ | | | | | | | | | If there is no partition numbered 1, we decide that there are no partitions at all. That may not be correct, since at least one Debian installed has just a single partition numbered 2. Continue searching up to partition 3, just in case. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini2023-05-1158-147/+380
|\ | | | | | | | | - Various fixes for Google chromebooks - Various minor enhancements for coreboot
| * x86: samus: Adjust TPL start and pre-reloc memory sizeSimon Glass2023-05-111-2/+2
| | | | | | | | | | | | | | | | Move the TPL up a little to make room for the refcode binary blob. Also increase the pre-relocation memory to make space for recent additions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: samus: Don't include audio and SATA in TPLSimon Glass2023-05-111-2/+2
| | | | | | | | | | | | | | These are not used in TPL so disable the drivers to save space. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Simplify cpu_jump_to_64bit_uboot()Simon Glass2023-05-111-27/+5
| | | | | | | | | | | | | | | | | | | | | | This copies the cpu_call64() function to memory address and then jumps to it. This seems to work correctly even when called from SPL, which is running from SPI flash. Drop the copy as it is not needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * spl: Commit MTRRs only in board_init_f_r()Simon Glass2023-05-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | We don't need to commit the SPI-flash MTRR change immediately, since it is now done in the board_init_f_r(). Also this causes chromebook_link64 to hang, presumably since we are still running from CAR (Cache-as-RAM) in SPL. Coral handles this OK, perhaps since it is running from a different memory area, but it has no effect on Coral anyway. Drop the extra mtrr_commit() in the SPL implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: spl: Avoid using init_cache_f_r() from SPLSimon Glass2023-05-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This function is used by U-Boot proper. It does not set up MTRRs when SPL is enabled, but we do want this done when it is called from SPL. In fact it is confusing to use the same function from SPL, since there are quite a few conditions there. All init_cache_f_r() really does is commit the MTRRs and set up the cache. Do this in the SPL's version of this function instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up address for loading U-Boot from SPLSimon Glass2023-05-111-10/+3
| | | | | | | | | | | | | | | | | | Use the binman symbols for this, to avoid hard-coding the value. We could use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to obtain the offset and size through the same mechanism. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: sysreset: Set up LPC only after relocationSimon Glass2023-05-111-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Probing LPC can cause PCI enumeration to take place, which significantly increases pre-relocation memory usage. Also, LPC is somtimes enabled directly by SPL. Adjust the logic to probe the LPC only after relocation. This allows chromebook_link64 to start up without a much larger CONFIG_SYS_MALLOC_F_LEN value. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: spl: Show debugging for BSSSimon Glass2023-05-111-0/+2
| | | | | | | | | | | | | | Show the area of memory cleared for BSS, when debugging is enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: mrc: Correct SPL debug messageSimon Glass2023-05-111-1/+1
| | | | | | | | | | | | | | | | SPL printf() does not normally support %#x so just use %x instead. Hex is expected in U-Boot anyway. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up availability of string functionsSimon Glass2023-05-112-2/+8
| | | | | | | | | | | | | | | | | | For now, just enable the fast-but-large string functions in 32-boot U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit builds since we only have 32-bit assembly. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Support debug UART in 64-bit modeSimon Glass2023-05-111-0/+7
| | | | | | | | | | | | | | | | The debug UART is already set up in SPL, so there is no need to do anything here. We must provide the (empty) function though. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: samus: Drop EFI_LOADERSimon Glass2023-05-111-0/+1
| | | | | | | | | | | | | | | | This adds a lot of code so that it cannot be built with the binary blobs. It is not used on this board. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Ensure LPC is available for GPIO baseSimon Glass2023-05-111-8/+9
| | | | | | | | | | | | | | | | | | | | | | The bd82x6x_get_gpio_base() does not work if the LPC is not set up. Probe it early to avoid this problem. In chromebook_link64 this problem shows up as an inability to read the GPIO straps for the memory type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * sf: Rename spi-nor-tiny functionsSimon Glass2023-05-111-8/+8
| | | | | | | | | | | | | | | | | | | | The 'tiny' SPI nor functions have the same name as their big brothers, which can be confusing. Use different names so it is clear which version is in the image. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * sf: Guard against zero erasesizeSimon Glass2023-05-111-1/+2
| | | | | | | | | | | | | | | | With tiny SPI flash the erasesize is 0 which can cause a divide-by-zero error. Check for this and return a proper error instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * binman: Support writing symbols for ucode etypesSimon Glass2023-05-113-4/+4
| | | | | | | | | | | | | | | | Allow symbol writing in these cases so that U-Boot can find the position and size of U-Boot at runtime. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: Emit the arch_cpu_init_dm() even only before relocationSimon Glass2023-05-1118-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | The original function was only called once, before relocation. The new one is called again after relocation. This was not the intent of the original call. Fix this by renaming and updating the calling logic. With this, chromebook_link64 makes it through SPL. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * coreboot: Enable ms commandSimon Glass2023-05-111-0/+1
| | | | | | | | | | | | | | This is useful when looking for tables in memory. Enable it for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: nvme: coreboot: Enable NVMeSimon Glass2023-05-111-0/+1
| | | | | | | | | | | | | | | | Enable support for NVMe storage devices. Update the driver to enable the bus master bit, since coreboot does not do that automatically. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * nvme: Enable PCI bus masteringSimon Glass2023-05-111-0/+5
| | | | | | | | | | | | | | | | U-Boot sets up devices ready for use, but coreboot does not. Enable this so that NVMe works OK from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Show unimplemented sysinfo tagsSimon Glass2023-05-113-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes coreboot adds new tags that U-Boot does not know about. These are silently ignored, but it is useful to at least know what we are missing. Add a way to collect this information. For Brya it shows: Unimpl. 38 41 37 34 42 40 These are: LB_TAG_PLATFORM_BLOB_VERSION LB_TAG_ACPI_CNVS LB_TAG_FMAP LB_TAG_VBOOT_WORKBUF LB_TAG_TYPE_C_INFO LB_TAG_BOARD_CONFIG Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Log function names and line numbersSimon Glass2023-05-111-0/+4
| | | | | | | | | | | | | | | | | | Turn these options on to make it easier to debug things. Also enable dhrystone so we can get some measure of performance. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Scan PCI after relocationSimon Glass2023-05-111-0/+1
| | | | | | | | | | | | | | | | | | Enable this so that PCI devices can be used correctly without needing to do a manual scan. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Document how to enable the debug UARTSimon Glass2023-05-111-0/+29
| | | | | | | | | | | | | | This is not obvious so add a little note about how it works. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Use a memory-mapped UARTSimon Glass2023-05-112-2/+0
| | | | | | | | | | | | | | | | | | | | | | This is much more common on modern hardware, so default to using it. This does not affect the normal UART, but does allow the debug UART to work, since it uses serial_out_shift(), etc. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * pci: coreboot: Don't read regions when bootingSimon Glass2023-05-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When U-Boot is the second-stage bootloader, PCI is already set up. We cannot read the regions from the device tree. There is no point anyway, since PCI devices have already been allocated according to the regions and it is not safe for U-Boot to make any changes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Fixes: f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()") Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow locating the UART from ACPI tablesSimon Glass2023-05-112-8/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When coreboot does not pass a UART in its sysinfo struct, there is no easy way to find it out. Since coreboot does not actually init the serial device when serial is disabled, it is not possible to make it add this information to the sysinfo table. Add a way to obtain this information from the DBG2 ACPI table, which is normally set up by coreboot. For now this only supports a memory-mapped 16550-style UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: coreboot: Collect the address of the ACPI tablesSimon Glass2023-05-115-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present any ACPI tables created by prior-stage firmware are ignored. It is useful to be able to view these in U-Boot. Pick this up from the sysinfo tables and display it with the cbsysinfo command. This allows the 'acpi list' command to work when booting from coreboot. Adjust the global_data condition so that acpi_start is available even if table-generation is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * acpi: Move the table-finding functions into the libarySimon Glass2023-05-114-39/+56
| | | | | | | | | | | | | | | | | | This is useful for other features. Move the function into library code so it can be used outside just the 'acpi' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * acpi: Create a new Kconfig for ACPISimon Glass2023-05-117-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have several Kconfig options for ACPI, but all relate to specific functions, such as generating tables and AML code. Add a new option which controls including basic ACPI library code, including the lib/acpi directory. This will allow us to add functions which are available even if table generation is not supported. Adjust the command to avoid a build error when ACPIGEN is not enabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * input: Flush the keyboard buffer before resetting itSimon Glass2023-05-111-0/+19
| | | | | | | | | | | | | | | | | | | | | | If U-Boot is not the first-stage bootloader the keyboard may already be set up. Make sure to flush any data before trying to reset it. This avoids a long timeout / hang. Add some comments and a log category while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Adjust search range for sysinfo tableSimon Glass2023-05-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Avoid searching starting at 0 since this memory may not be available, e.g. if protection against NULL-pointer access is enabled. The table cannot be there anyway, since the first 1KB of memory was originally used for the interrupt table and coreboot avoids it. Start at 0x400 instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * mtrr: Don't show an invalid CPU numberSimon Glass2023-05-111-1/+2
|/ | | | | | | | When U-Boot did not do the MP init, we don't get an actual CPU number here. Skip printing it in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'u-boot-rockchip-20230509' of ↵Tom Rini2023-05-09139-413/+3056
|\ | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-rockchip - Rockchip NFC driver update and dev addr pointer api update; - use standard dr_mode for usb driver; - rock pi boards dts update; - Add rk3566 Anbernic boards; - Misc fixes for drivers;
| * clk: rockchip: rk3588: add hardcoded assigned clocks valuesEugen Hristev2023-05-091-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CRU is being probed with a default set of assigned clocks, which are not implemented in the driver at all. Hence, when clk_set_defaults is called, it fails with ENOENT. This would not be a problem, as the CRU still handles all the required clocks, and the assigned clocks are default configs which are preprogrammed or not required for Uboot operations. However, the rockchip reset driver is being bound by the same DT node as CRU, as the reset driver has no DT node. But, when probing the reset node, it will call again the clk_set_defaults for the CRU node, and failing because of missing those specific clocks in the rk3588 clock driver. To avoid this, simply implement a basic set/get that will just return success and the default corresponding rate for the required assigned clocks. As those clocks were not supported in Uboot, not required for Uboot operations, there is no need to do any different kind of initialization. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: handle peripheral as well as otg dr_modeJohn Keeping2023-05-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | The OTG port is identified by inspecting the "dr_mode" property which is expected to be "otg" for this port. But it will work just as well as a device controller when dr_mode is set to "peripheral", which may be required if the mode detection pin is not set up correctly and the device controller needs to be programmed to override this. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: use standard dr_mode parsing functionJohn Keeping2023-05-091-3/+9
| | | | | | | | | | | | | | | | | | | | | | Instead of duplicating the string values here, use usb_get_dr_mode() to handle the property lookup and converting the values to an enum. This is implemented with a switch in preparation for the next patch which adds extra handling for peripheral mode. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rockchip: rock-3a: drop u-boot,spl-boot-orderFUKAUMI Naoki2023-05-091-1/+0
| | | | | | | | | | | | | | use common one defined in rk356x-u-boot.dtsi. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * arm: dts: rk356x: Makefile: sortFUKAUMI Naoki2023-05-091-1/+1
| | | | | | | | | | | | | | sort alphanumerically. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * doc: rockchip: update list of Radxa ROCK (Pi) 4 boardsFUKAUMI Naoki2023-05-091-1/+4
| | | | | | | | | | | | | | add Radxa ROCK (Pi) 4 variants. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * configs: rockchip: add Radxa ROCK 4C+FUKAUMI Naoki2023-05-091-0/+97
| | | | | | | | | | | | | | add defconfig for Radxa ROCK 4C+. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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