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* imx8mq_evk: Add myself as a co-maintainerFabio Estevam2019-03-131-0/+1
| | | | | | | I would like to help maintaining this board. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* imx8mq_evk: Move CONFIG_ENV_IS_IN_MMC to KconfigFabio Estevam2019-03-132-1/+1
| | | | | | | | | | Currently the command "saveenv" is not available. The CONFIG_ENV_IS_IN_MMC symbol has been converted to Kconfig, so fix the problem by moving it to the defconfig. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* mx6sabreauto: README: Adjust the binary name after DM conversionFabio Estevam2019-03-131-6/+6
| | | | | | | | After the conversion to DM the U-Boot binary is called u-boot-dtb.imx, so fix the README file accordingly. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* mx6sabresd: README: Adjust the binary name after DM conversionFabio Estevam2019-03-131-9/+9
| | | | | | | | After the conversion to DM the U-Boot binary is called u-boot-dtb.imx, so fix the README file accordingly. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* imx: mx6qsabrelite: Update the SabreLite READMEMartyn Welch2019-03-131-36/+83
| | | | | | | | | | | | | | | The information in the SabreLite README is inaccurate and sparse. The upstream U-Boot can boot the SabreLite from SPI-NOR. Additionally, the freely available imx_loader tool can be easily used to boot a board with a corrupted SPI, the official Freescale/NXP manufacturing tools are not required. Reformat the document, adding a description of how to boot from SPI-NOR and adding a brief description of how to recover the board should the SPI-NOR be corrupted using imx_loader. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
* imx8mq_evk/README: fix DDR training firmware pathBaruch Siach2019-03-131-1/+1
| | | | | | | | | Remove a redundant directory level. Reported-by: Ofer Heifetz <ofer.heifetz@valens.com> Tested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* imx8mq_evk/README: add missing firmware extract stepBaruch Siach2019-03-131-0/+1
| | | | | | Tested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* warp7: Fix the write to the LDOGCTL PMIC registerFabio Estevam2019-03-131-1/+1
| | | | | | | | | | | | | The third parameter of the pmic_clrsetbits() function is the mask to the register and the correct mask is 1 not 0. Since the LDOGCTL only contains a single valid bit (bit 0), we can use pmic_reg_write() and write 1 directly, which fixes the problem in a simpler way and use the original pmic function that was used prior to the DM PMIC conversion. Fixes: 8ba377321c86 ("arm: imx7s-warp: Convert to DM PMIC") Signed-off-by: Fabio Estevam <festevam@gmail.com>
* mx6ul_14x14_evk: Simplify the PMIC register writesFabio Estevam2019-03-131-6/+3
| | | | | | | | There is no need to store the values written to the PMIC inside the 'reg' variable. Make it simpler by writing the values directly. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* warp7: Remove unneeded headers after DM conversionFabio Estevam2019-03-131-4/+0
| | | | | | | After DM conversion the I2C and MMC related board codes have been removed, so remove the corresponding header files as well. Signed-off-by: Fabio Estevam <festevam@gmail.com>
* warp7: README: Adjust the binary name after DM conversionFabio Estevam2019-03-131-6/+6
| | | | | | | | | After the conversion to DM the U-Boot binary is called u-boot-dtb.imx, so fix the README file accordingly. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
* imx: ventana: added support for 16bit 8Gb density (1GiB) DRAMTim Harvey2019-03-131-0/+5
| | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: ventana: hexdump invalid EEPROM dataTim Harvey2019-03-134-0/+13
| | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* ARM: liteboard: use random ethaddrMarcin Niestroj2019-03-131-0/+1
| | | | | | | There is no ethaddr assigned to each board, so we need to use random value in order to use network. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
* ARM: liteboard: move towards driver model and device-tree bootMarcin Niestroj2019-03-132-37/+10
| | | | | | | | | This patch mostly enables DM drivers in board defconfig and all their dependencies. Additionally we remove USB code that is on longer executed after enabling CONFIG_DM_USB. Enable CONFIG_PINCTRL, so we can get rid of ethernet pin configuration. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
* pico-imx6ul: README: Adjust the binary name after DM conversionFabio Estevam2019-03-131-7/+7
| | | | | | | | After the conversion to DM the U-Boot binary is called u-boot-dtb.imx, so fix the README file accordingly. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* pico-imx6ul: Convert to DM_PMICFabio Estevam2019-03-135-58/+35
| | | | | | | | | | | Convert to use DM_PMIC for the PFUZE3000. Since this PMIC is under an I2C bus, conver to DM_I2C as well. Also, since I2C is not used in SPL, remove CONFIG_SPL_I2C_SUPPORT to avoid build warnings. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* pico-imx6ul: Convert to CONFIG_DM_GPIOFabio Estevam2019-03-134-0/+10
| | | | | | | | | | Convert to CONFIG_DM_GPIO. Also, DM GPIO requires gpio_request() to be called explicitly before doing any gpio operation, so do as requested. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* pico-imx6ul: Convert to DM MMCFabio Estevam2019-03-135-34/+5
| | | | | | | | | Select CONFIG_DM_MMC=y in order to support MMC driver model. This allows the MMC board related code to be removed. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* pico-imx6ul: Select CONFIG_OF_CONTROLFabio Estevam2019-03-133-3/+6
| | | | | | | | Select CONFIG_OF_CONTROL and the appropriate device tree files in preparation for converting to driver model. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* pico-imx6ul: Import dts files from kernelFabio Estevam2019-03-133-0/+658
| | | | | | | | Import the device tree files from kernel 5.0-rc6 in preparation for driver model conversion. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* imx8mq_evk_defconfig: Enable pinctrl driverChris Spencer2019-03-131-0/+1
| | | | | | | | | | | | | The Ethernet controller is not able to initialise correctly without the pinctrl driver. This config setting was enabled in the initial version of this file, but was removed by a savedefconfig resync because the parameter did not actually exist at that point. Fixes: 1bac199e8c87 ("configs: Resync with savedefconfig") Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* pinctrl: add imx8m driverPeng Fan2019-03-133-0/+51
| | | | | | Add i.mx8m pinctrl driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2019-03-119-1/+22
|\ | | | | | | | | - axp818 fix - fix warnings for ethernet clock code
| * clk: sunxi: h3: Implement EPHY CLK and RESETJagan Teki2019-03-091-0/+4
| | | | | | | | | | | | | | | | | | | | EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * clk: sunxi: Implement EMAC, GMAC clocks, resetsJagan Teki2019-03-096-0/+15
| | | | | | | | | | | | | | | | | | | | | | - Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * clk: sunxi: Implement A10 EMAC clocksJagan Teki2019-03-092-0/+2
| | | | | | | | | | | | | | | | Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC. Which would eventually used in sunxi_emac.c driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * power: axp818: Fix typo in axp_set_dldoOndrej Jirman2019-03-081-1/+1
| | | | | | | | | | | | | | | | | | Fix typo in axp_set_dldo() so that it correctly uses AXP818_DLDO1_CTRL register to configure the voltage instead of setting AXP818_ELDO1_CTRL register which is obviously incorrect. Signed-off-by: Ondřej Jirman <megous@megous.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2019-03-118-5/+51
|\ \ | | | | | | | | | | | | - ACPI changes and fixes to Intel Tangier/Edison - i8254 beeper fixes
| * | x86: crownbay: Enable the beeper sound driverBin Meng2019-03-112-0/+4
| | | | | | | | | | | | | | | | | | | | | Use the i8254 sound driver to support creating simple beeps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: coreboot: Add the missing pc speaker node in the device treeBin Meng2019-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This is currently missing and without it the i8254 beeper driver won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Add a dtsi file for the pc speakerBin Meng2019-03-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | The pc speaker driven by the i8254 is generic enough to deserve a single dtsi file to be included by boards that use it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Make sure i8254 is setup correctly before generating beepsBin Meng2019-03-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i8254 timer control IO port (0x43) should be setup correctly by using PIT counter 2 to generate beeps, however in U-Boot other codes like TSC driver utilizes PIT for TSC frequency calibration and configures the counter 2 to a different mode that does not beep. Fix this by always ensuring the PIT counter 2 is correctly initialized so that the i8254 beeper driver works as expected. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: edison: Add the rest of UARTs present on boardAndy Shevchenko2019-03-101-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Edison has three UART ports, i.e. port 0 - Bluetooth port 1 - auxiliary, available for general purpose use port 2 - debugging, usually console output is here Enable all of them for future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: edison: Use proper number of serial interfaceAndy Shevchenko2019-03-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The console is actually serial #2. When we would like to enable other ports, this would be not okay to mess up with the ordering. Thus, fix the number of default console interface to be 2. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Not every platform has serial console a first deviceAndy Shevchenko2019-03-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We may not do an assumption that current console device is always a first of UCLASS_SERIAL one. For example, on properly described Intel Edison board the console UART is a third one. Use current serial device as described in global data. Fixes: a61cbad78e67 ("dm: serial: Adjust serial_getinfo() to use proper API") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Add DMA descriptors for I2C1 on Intel TangierAndy Shevchenko2019-03-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Note, I2C6, which is available to user, has no DMA request lines connected. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Add DMA descriptors for SPI5 on Intel TangierAndy Shevchenko2019-03-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-03-106-77/+49
|\ \ \ | | | | | | | | | | | | - Arria10 DRAM fixes and Gen5 cache fixes
| * | | ddr: socfpga: Clean up ddr_setup()Marek Vasut2019-03-091-28/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ddr: socfpga: Clean up EMIF resetMarek Vasut2019-03-091-26/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ddr: socfpga: Fix EMIF clear timeoutMarek Vasut2019-03-091-14/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Fix A10 SoCDK KconfigMarek Vasut2019-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig checked for SoCFPGA Arria10 as a platform, instead of checking for specific board configuration, which works with one single platform in tree, but not with multiple. Fix it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offsetMarek Vasut2019-03-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POSMarek Vasut2019-03-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not used anywhere, so drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Disable D cache in SPLMarek Vasut2019-03-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootrom seems to leave the D-cache in messed up state, make sure the SPL disables it so it can not interfere with operation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ddr: socfpga: Fix newline in debug print on A10Marek Vasut2019-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The debug print is missing a newline, add it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ddr: socfpga: Fix IO in Arria10 DDR driverMarek Vasut2019-03-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: fix data and tag latency values for pl310 cache controllerDinh Nguyen2019-03-091-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | The values for the data and tag latency settings on the PL310 caches controller is an (n-1). For example, the "arm,tag-latency" is specified as <1 1 1>, so the values that should be written to register should be 0x000. And for the "arm,data-latency" specified as <2 1 1>, the register value should be 0x010. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-03-1013-100/+57
|\ \ \ | |/ / |/| | | | | - More gen2/gen3 fixes
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