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* configs: kirkwood: ds109: switch to DM_I2CChris Packham2018-08-071-0/+2
| | | | | | | Enable DM_I2C and I2C_MVTSWI for the ds109 board. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mvebu: clearfog: use kconfig symbols to select boot deviceBaruch Siach2018-08-061-14/+2
| | | | | | | | This allows selection of the boot device at build time without source code modification. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* mvebu: support UART boot imageBaruch Siach2018-08-062-0/+6
| | | | | | | | The kwboot utility can use the generated image to boot mvebu SoCs from UART. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* mvebu: select boot device at SoC levelBaruch Siach2018-08-0617-155/+34
| | | | | | | | | | | | | | | Move the gdsys Controlcenter DC specific build time kwbimage.cfg generation code into the mach-mvebu/ directory to be shared by all 32bit mvebu platforms. Remove board specific kwbimage.cfg files, and use the generated one instead. These files are all identical, with two exceptions. Clearfog and Helios4 use the sdio boot device, whereas all others use spi. Update the defconfigs for the exceptional boards to generate the same kwbimage.cfg as before. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* mvebu: consolidate SPL boot device config symbolsBaruch Siach2018-08-065-36/+8
| | | | | | | | | | | Use MVEBU_SPL_BOOT_DEVICE_* to select between SPI and MMC, instead of board specific symbols. This commit enables the boot device selection menu to all mvebu platforms, but it is only effective on Turris Omnia and gdsys Controlcenter DC platforms. A following commit will enable boot selection for other platforms. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* mvebu: a38x: drop duplicate platform id symbolsBaruch Siach2018-08-062-12/+3
| | | | | | | Use generic mvebu Kconfig symbols like all other mvebu boards. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* mvebu: turris_omnia: use u-boot-spl-dtb.binBaruch Siach2018-08-061-1/+1
| | | | | | | | | u-boot-spl.bin and u-boot-spl-dtb.bin are identical when building the turris_omnia_defconfig. This commit makes Turris Omnia consistent with all other mvebu boards. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2018-08-045-3/+476
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| * arm: sunxi: Allwinner A10 SPI driverStefan Mavrodiev2018-08-033-0/+462
| | | | | | | | | | | | | | | | Add spi driver for sun4i, sun5i and sun7i SoCs. The driver is adapted from mailine kernel. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: kirkwood: add orion-spi compatible stringChris Packham2018-08-031-0/+8
| | | | | | | | | | | | | | | | | | | | This matches the compatible string used by the Linux kernel. This will allow u-boot to use the same device tree files. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> [jagan: use armada instead of orion on .data] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: kirkwood: Get drvdata in .ofdata_to_platdataJagan Teki2018-08-031-3/+5
| | | | | | | | | | | | | | | | Get the is_errata_50mhz_ac in .ofdata_to_platdata, and reuse it in .set_mode this can eventually initialized dt code at once and adding room to add platdata. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: add spi flash id s25fl128lClément Laigle2018-08-031-0/+1
| | | | | | | | | | | | | | | | | | Add support for SPANSION s25fl128l Signed-off-by: Clément Laigle <c.laigle@catie.fr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: fixed , at the end of } ] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2018-08-0446-61/+2560
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| * | board: sun50i: h6: Add OrangePi One Plus initial supportJagan Teki2018-07-314-0/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OrangePi One Plus is Allwinner H6 based open-source SBC, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 1GB LPDDR3 RAM - AXP805 PMIC - 1Gbps GMAC via RTL8211 - USB 2.0 Host, OTG - HDMI port - 5V/2A DC power supply Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * | mtd: nand: sunxi: Return on set_feature only when not ENOTSUPPMylène Josserand2018-07-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Return the error code of the set_features function only if the error code is not ENOTSUPP. Otherwise, if this function is not supported, it will return and fail to initialize the NAND. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
| * | mtd: nand: nand_base: Convert EINVAL into ENOTSUPPMylène Josserand2018-07-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Convert the EINVAL error into ENOTSUPP when the GET/SET_FEATURES is not supported. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
| * | configs: sunxi: Drop CONFIG_SUNXI_USB_PHYSJagan Teki2018-07-317-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | Now number of PHY on Allwinner is handling via dt data, drivers at phy/allwinner/phy-sun4i-usb.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | phy: sun4i-usb: Update PHY#3 rst_mask only for H3_H5Jagan Teki2018-07-311-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Only H3 and H5 have 4 PHYS so restrict rst_mask only for them by checking PHY id as 3 and update the proper bits. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | phy: sun4i-usb: Remove usb_clk_cfg set in probeJagan Teki2018-07-311-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | usb_clk_cfg is setting CTRL_PHYGATE bit value in probe which is BIT 0 for sun4i, 6i and 8 for a83t but all these were handling in phy ops init exit calls. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | phy: sun4i-usb: Call phy_passby even for PHY#0Jagan Teki2018-07-311-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On newer Allwinner SoC, there is a pair of EHCI/OHCI USB hosts for OTG host mode. USB PHY passby must be configured for its corresponding PHY. so we can call for PHY#0. on the other hand in past usb-phy code the same thing can be restricted for Lower SoC's, other than H3/H5/A64. Now there is no need to restrict usb passby since the phy driver is DT enabled, and the respective phy calls will trigger based DT information initiated by the drivers. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | video: sunxi: de2: fix SimpleFB node creation when DE2 not probedIcenowy Zheng2018-07-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes when a monitor without EDID information is plugged, the DE2 won't be probed (because of lack of timing information), but the HDMI node is probed, thus a SimpleFB node with invalid information will be populated. Also detect whether DE2 is probed when creating SimpleFB node. Fixes: be5b96f0e411 ("sunxi: setup simplefb for Allwinner DE2") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: add support for Pine H64 boardIcenowy Zheng2018-07-314-0/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features 1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port and a mPCIE slot. Add support for it. The device tree is from Linux next-20180720. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: add support for Allwinner H6 SoCIcenowy Zheng2018-07-318-2/+546
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe interfaces. This patch adds support for it. The corresponding DTSI file, from Linux next-20180720, is also introduced. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: add DRAM support to H6Icenowy Zheng2018-07-315-0/+1061
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo. Both the controller and the PHY seem to be originate from DesignWare, and are similar to the ones in ZynqMP SoCs. This commit introduces an initial DRAM driver for H6, which contains only LPDDR3 support. The currently known SBCs with H6 all come with LPDDR3 memory, including Pine H64 and several Orange Pi's. The BSP DRAM initialization code is closed source and violates GPL. Code in this commit is written by experimenting, referring the code/document of other users of the IPs (mainly the ZynqMP, as it's the only found PHY reference) and disassebling the BSP blob. Thanks for Jernej Skrabec for review and fix some issues in this driver (including the most critical one which made it to work), and rewrite some code from register dump! Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: add MMC support for H6Icenowy Zheng2018-07-313-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with the MMC2 come with the capability to do crypto by EMCE. Add MMC support for H6. EMCE support is not added yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: add UART0 setup for H6Icenowy Zheng2018-07-312-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UART0 on H6 is available at PH bank (and PF bank, but the PF one is muxed with SD card). Add pinmux configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: use sun6i-style watchdog for H6Icenowy Zheng2018-07-312-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The H6 SoC has a sun6i-style watchdog in its timer part. Enable the usage of it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: add clock code for H6Icenowy Zheng2018-07-314-0/+417
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Allwinner H6 SoC has a brand new CCU layout. Add clock code for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: change GIC address on H6Icenowy Zheng2018-07-311-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the Allwinner H6 chip has a new memory map, its GIC MMIO address is thus different. Change the address on H6. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: add config for SPL at 0x20000 on H6Icenowy Zheng2018-07-311-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the new Allwinner H6 SoC, the SRAM A2 address (SPL load address) is at 0x20000, which is different with any old Allwinner SoCs. Add SPL position and size configuration for this. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: change ATF position for H6Icenowy Zheng2018-07-311-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H6 has different SRAM A2 address, so the ATF load address is also different. Add judgment code to sunxi 64-bit FIT generation script. It will judge the SoC by the device tree's name. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: change RMR64's RVBAR address for H6Icenowy Zheng2018-07-312-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner H6 has a different RVBAR address with A64/H5. Add conditional RVBAR configuration into the code which does RMR switch. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: add basic memory map definitions of H6 SoCIcenowy Zheng2018-07-312-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner H6 SoC come with a totally new memory map. Add basical definition of the new memory map into a header file, and let the cpu.h header include it in the situation of H6. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESSIcenowy Zheng2018-07-313-22/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored to support this new configuration. Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM A1 in the memory map. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
| * | sunxi: enable SATA on Banana Pi M2 BerrySimon Baatz2018-07-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Banana Pi M2 Ultra and M2 Berry are very similar boards. SATA can be enabled exactly the same as for M2 Ultra introduced in commit daa8b75a5527 ("sunxi: enable SATA on Banana Pi M2 Ultra"). Signed-off-by: Simon Baatz <gmbnomis@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | | clk: clk_set_default: accept no-op skip fieldsNeil Armstrong2018-08-041-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Assigned Clock parents and rates misses the fact that a "0" entry can be passed to skip setting a parent or rate of an assigned clock as described in the Linux clock bindings at [1]. This patch simply skips the clock reparenting if the DT parsing returns -ENOENT and the clock rate setting if "0" is passed as clock rate. [1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/clock/clock-bindings.txt#L135 Fixes: f4fcba5c5baa "clk: implement clk_set_defaults()" Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mailmap: Update mail address (lukma)Lukasz Majewski2018-08-041-0/+1
| | | | | | | | | | | | | | | | | | Update my e-mail address from samsung.com to denx.de Signed-off-by: Lukasz Majewski <lukma@denx.de>
* | | ARM: dts: stm32: remove cd-inverted for stm32429i-evalPatrice Chotard2018-08-031-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | As cd-inverted property is no more used by arm_pl180_mmci driver, remove it. Update cd-gpios active level accordingly. Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | | mmc: arm_pl180_mmci: Remove cd_inverted host's struct fieldPatrice Chotard2018-08-032-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As platform uses GPIOs for card detection, it's simpler and more readable to use GPIO_ACTIVE_(LOW|HIGH) in the gpio flags instead of using the cd-inverted property. Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | | mmc: arm_pl180_mmci: Add missing clk_freePatrice Chotard2018-08-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add missing clk_free() call in case of failure when enabling the clock. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mmc: arm_pl180_mmci: Update to support CONFIG_BLKPatrice Chotard2018-08-031-27/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config flag CONFIG_BLK becomes mandatory, update arm_pl180_mmci to support this config. This driver is used by STM32Fx and by Vexpress platforms. Only STM32Fx are DM ready. No DM code is isolated and will be removed easily when wexpress will be converted to DM. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | | configs: stm32f469-disco: Enable CONFIG_BLKPatrice Chotard2018-08-031-1/+0
| | | | | | | | | | | | | | | | | | CONFIG_BLK config flag becomes mandatory, enable it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | | configs: stm32f746-disco: Enable CONFIG_BLKPatrice Chotard2018-08-031-1/+0
| | | | | | | | | | | | | | | | | | | | | CONFIG_BLK config flag becomes mandatory, enable it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | configs: stm32f429-evaluation: Enable CONFIG_BLKPatrice Chotard2018-08-031-1/+0
| | | | | | | | | | | | | | | | | | CONFIG_BLK config flag becomes mandatory, enable it. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | | docproc: RemoveTom Rini2018-08-033-590/+0
| | | | | | | | | | | | | | | | | | | | | Now that we have moved to Sphinx documentation we don't need the docproc app anymore, remove. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | bootcount: Fix misaligned cache operationAlex Kiernan2018-08-031-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1947c2d2a0 introduces cache line flushes for the bootcounter, but if the start address is not aligned then the flush causes warnings of the form: CACHE: Misaligned operation at range [4030b7fc, 4030b83c] Align both the start and end of the buffer (possibly crossing multiple lines). Fixes: 1947c2d2a0 ("bootcount: flush after storing the bootcounter") Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | armv8: make SPL exception vectors optionalAndre Przywara2018-08-033-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even though the exception vector table is a fundamental part of the ARM architecture, U-Boot mostly does not make real use of it, except when crash dumping. But having it in takes up quite some space, partly due to the architectural alignment requirement of 2KB. Since we don't take special care of that, the compiler adds a more or less random amount of padding space, which increases the image size quite a bit, especially for the SPL. On a typical Allwinner build this is around 1.5KB of padding, plus 1KB for the vector table (mostly padding space again), then some extra code to do the actual handling. This amounts to almost 10% of the maximum image size, which is quite a lot for a pure debugging feature. Add a Kconfig symbol to allow the exception vector table to be left out of the build for the SPL. For now this is "default y" for everyone, but specific defconfigs, platforms or .config files can opt out here at will, to mitigate the code size pressure we see for some SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | armv8: Reduce exception handling codeAndre Przywara2018-08-031-50/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arm64 exception handling code is quite big, mostly due to architectural alignment requirements. Each exception entry spans 32 instructions, which sounds generous, but is too small to fit all of the save/branch/restore code in there. So at the moment we use only four instructions, branching into shared save and restore routines. To not leave the space for those remaining 28 instructions wasted, let's split the save and restore routines and stuff them into the gaps. This saves about 250 bytes of code, which is helpful for those tight SPLs. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | ti_omap3_common: Add CONFIG_SYS_NS16550_COMx entriesAdam Ford2018-08-033-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several boards do not use the default UART3, so they do a check for ifdef CONFIG_SPL_BUILD and enable the pointer for CONFIG_SYS_NS16550_COMx to point to OMAP34XX_UARTx. Let's consoldate this all into one place, and remove them from the individual boards. Signed-off-by: Adam Ford <aford173@gmail.com>
* | | configs: stm32mp15: enable ADCFabrice Gasnier2018-08-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable ADC on stm32mp15. - CONFIG_CMD_ADC - CONFIG_STM32_ADC Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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