summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* pico-imx6ul: Convert to CONFIG_DM_GPIOFabio Estevam2019-03-134-0/+10
| | | | | | | | | | Convert to CONFIG_DM_GPIO. Also, DM GPIO requires gpio_request() to be called explicitly before doing any gpio operation, so do as requested. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* pico-imx6ul: Convert to DM MMCFabio Estevam2019-03-135-34/+5
| | | | | | | | | Select CONFIG_DM_MMC=y in order to support MMC driver model. This allows the MMC board related code to be removed. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* pico-imx6ul: Select CONFIG_OF_CONTROLFabio Estevam2019-03-133-3/+6
| | | | | | | | Select CONFIG_OF_CONTROL and the appropriate device tree files in preparation for converting to driver model. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* pico-imx6ul: Import dts files from kernelFabio Estevam2019-03-133-0/+658
| | | | | | | | Import the device tree files from kernel 5.0-rc6 in preparation for driver model conversion. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* imx8mq_evk_defconfig: Enable pinctrl driverChris Spencer2019-03-131-0/+1
| | | | | | | | | | | | | The Ethernet controller is not able to initialise correctly without the pinctrl driver. This config setting was enabled in the initial version of this file, but was removed by a savedefconfig resync because the parameter did not actually exist at that point. Fixes: 1bac199e8c87 ("configs: Resync with savedefconfig") Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* pinctrl: add imx8m driverPeng Fan2019-03-133-0/+51
| | | | | | Add i.mx8m pinctrl driver. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2019-03-119-1/+22
|\ | | | | | | | | - axp818 fix - fix warnings for ethernet clock code
| * clk: sunxi: h3: Implement EPHY CLK and RESETJagan Teki2019-03-091-0/+4
| | | | | | | | | | | | | | | | | | | | EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * clk: sunxi: Implement EMAC, GMAC clocks, resetsJagan Teki2019-03-096-0/+15
| | | | | | | | | | | | | | | | | | | | | | - Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * clk: sunxi: Implement A10 EMAC clocksJagan Teki2019-03-092-0/+2
| | | | | | | | | | | | | | | | Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC. Which would eventually used in sunxi_emac.c driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * power: axp818: Fix typo in axp_set_dldoOndrej Jirman2019-03-081-1/+1
| | | | | | | | | | | | | | | | | | Fix typo in axp_set_dldo() so that it correctly uses AXP818_DLDO1_CTRL register to configure the voltage instead of setting AXP818_ELDO1_CTRL register which is obviously incorrect. Signed-off-by: Ondřej Jirman <megous@megous.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | Merge git://git.denx.de/u-boot-x86Tom Rini2019-03-118-5/+51
|\ \ | | | | | | | | | | | | - ACPI changes and fixes to Intel Tangier/Edison - i8254 beeper fixes
| * | x86: crownbay: Enable the beeper sound driverBin Meng2019-03-112-0/+4
| | | | | | | | | | | | | | | | | | | | | Use the i8254 sound driver to support creating simple beeps. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: coreboot: Add the missing pc speaker node in the device treeBin Meng2019-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This is currently missing and without it the i8254 beeper driver won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Add a dtsi file for the pc speakerBin Meng2019-03-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | The pc speaker driven by the i8254 is generic enough to deserve a single dtsi file to be included by boards that use it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Make sure i8254 is setup correctly before generating beepsBin Meng2019-03-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i8254 timer control IO port (0x43) should be setup correctly by using PIT counter 2 to generate beeps, however in U-Boot other codes like TSC driver utilizes PIT for TSC frequency calibration and configures the counter 2 to a different mode that does not beep. Fix this by always ensuring the PIT counter 2 is correctly initialized so that the i8254 beeper driver works as expected. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: edison: Add the rest of UARTs present on boardAndy Shevchenko2019-03-101-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Edison has three UART ports, i.e. port 0 - Bluetooth port 1 - auxiliary, available for general purpose use port 2 - debugging, usually console output is here Enable all of them for future use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: edison: Use proper number of serial interfaceAndy Shevchenko2019-03-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The console is actually serial #2. When we would like to enable other ports, this would be not okay to mess up with the ordering. Thus, fix the number of default console interface to be 2. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Not every platform has serial console a first deviceAndy Shevchenko2019-03-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We may not do an assumption that current console device is always a first of UCLASS_SERIAL one. For example, on properly described Intel Edison board the console UART is a third one. Use current serial device as described in global data. Fixes: a61cbad78e67 ("dm: serial: Adjust serial_getinfo() to use proper API") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Add DMA descriptors for I2C1 on Intel TangierAndy Shevchenko2019-03-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Note, I2C6, which is available to user, has no DMA request lines connected. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: acpi: Add DMA descriptors for SPI5 on Intel TangierAndy Shevchenko2019-03-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Tangier SoC has a general purpose DMA which can serve to speed up communications on SPI and I2C serial buses. Provide DMA descriptors to utilize this capability in the future. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-03-106-77/+49
|\ \ \ | | | | | | | | | | | | - Arria10 DRAM fixes and Gen5 cache fixes
| * | | ddr: socfpga: Clean up ddr_setup()Marek Vasut2019-03-091-28/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ddr: socfpga: Clean up EMIF resetMarek Vasut2019-03-091-26/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ddr: socfpga: Fix EMIF clear timeoutMarek Vasut2019-03-091-14/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Fix A10 SoCDK KconfigMarek Vasut2019-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig checked for SoCFPGA Arria10 as a platform, instead of checking for specific board configuration, which works with one single platform in tree, but not with multiple. Fix it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offsetMarek Vasut2019-03-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POSMarek Vasut2019-03-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not used anywhere, so drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: Disable D cache in SPLMarek Vasut2019-03-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootrom seems to leave the D-cache in messed up state, make sure the SPL disables it so it can not interfere with operation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ddr: socfpga: Fix newline in debug print on A10Marek Vasut2019-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The debug print is missing a newline, add it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ddr: socfpga: Fix IO in Arria10 DDR driverMarek Vasut2019-03-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * | | ARM: socfpga: fix data and tag latency values for pl310 cache controllerDinh Nguyen2019-03-091-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | The values for the data and tag latency settings on the PL310 caches controller is an (n-1). For example, the "arm,tag-latency" is specified as <1 1 1>, so the values that should be written to register should be 0x000. And for the "arm,data-latency" specified as <2 1 1>, the register value should be 0x010. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-03-1013-100/+57
|\ \ \ | |/ / |/| | | | | - More gen2/gen3 fixes
| * | ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3NEugeniu Rosca2019-03-091-99/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2019.01 commit cbff9f80cedd ("ARM: dts: rmobile: Sync Gen3 DTs with Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi. Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is equivalent to partially reverting below v2019.01 commits: - f529bc551b6d ("ARM: dts: rmobile: Extract USB nodes on M3N") - 830b94f76867 ("ARM: dts: rmobile: Extract SDHI nodes on M3N") Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously: - not needed if no U-boot-specific changes are needed in those nodes. - potentially dangerous/error-prone, since the duplicated properties override the properties originally defined in <soc>.dtsi. One possible consequence is that <soc>.dtsi is getting an update from Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation, the obsolete property values from <soc>-u-boot.dtsi will take precedence masking some of the <soc>.dtsi updates, potentially leading to all kind of obscure issues. Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user" of r8a77965-u-boot.dtsi) before and after the patch (slightly reformatted to avoid 'git am/apply' issues and to reduce the width). What below output means is there is already a mismatch in some of SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in r8a77965-u-boot.dtsi. $> dtdiff before-r8a77965-salvator-x-u-boot.dtb \ after-r8a77965-salvator-x-u-boot.dtb --- /dev/fd/63 2019-03-09 12:57:40.877963983 +0100 +++ /dev/fd/62 2019-03-09 12:57:40.877963983 +0100 @@ -1471,7 +1471,7 @@ bus-width = <0x4>; cd-gpios = <0x51 0xc 0x1>; clocks = <0x6 0x1 0x13a>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa5 0x4>; max-frequency = <0xc65d400>; pinctrl-0 = <0x4d>; @@ -1492,7 +1492,7 @@ sd@ee120000 { clocks = <0x6 0x1 0x139>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa6 0x4>; max-frequency = <0xbebc200>; power-domains = <0x1 0x20>; @@ -1504,7 +1504,7 @@ sd@ee140000 { bus-width = <0x8>; clocks = <0x6 0x1 0x138>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; fixed-emmc-driver-type = <0x1>; interrupts = <0x0 0xa7 0x4>; max-frequency = <0xbebc200>; @@ -1526,7 +1526,7 @@ bus-width = <0x4>; cd-gpios = <0x5a 0xf 0x1>; clocks = <0x6 0x1 0x137>; - compatible = "renesas,sdhi-r8a77965"; + compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi"; interrupts = <0x0 0xa8 0x4>; max-frequency = <0xc65d400>; pinctrl-0 = <0x56>; @@ -1868,14 +1868,14 @@ usb-phy@ee0a0200 { #phy-cells = <0x0>; - clocks = <0x6 0x1 0x2be>; + clocks = <0x6 0x1 0x2bf>; compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy"; phandle = <0x47>; pinctrl-0 = <0x4c>; pinctrl-names = "default"; power-domains = <0x1 0x20>; reg = <0x0 0xee0a0200 0x0 0x700>; - resets = <0x6 0x2be>; + resets = <0x6 0x2bf>; status = "okay"; }; Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
| * | ARM: rmobile: rcar-gen3: Activate bootm_sizeEugeniu Rosca2019-03-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2019.01 commit 07a8060a1277 ("ARM: rmobile: Convert to bootm_size") attempted converting to bootm_size of 256 MiB below targets: - include/configs/alt.h - include/configs/gose.h - include/configs/koelsch.h - include/configs/lager.h - include/configs/porter.h - include/configs/rcar-gen3-common.h - include/configs/silk.h - include/configs/stout.h The update didn't fully work on R-Car3 due to the CONFIG_SYS_BOOTMAPSZ=8MiB definition left by v2016.09 commit e525d34b476e ("ARM: rmobile: Add support salvator-x board"), which is explained in below README excerpt: ----8<---- CONFIG_SYS_BOOTMAPSZ: [..] If CONFIG_SYS_BOOTMAPSZ is undefined, then the value in "bootm_size" will be used instead. ----8<---- Allow the original commit to accomplish its purpose on R-Car3 targets by removing the CONFIG_SYS_BOOTMAPSZ definition. Fixes: 07a8060a1277 ("ARM: rmobile: Convert to bootm_size") Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
| * | ARM: rmobile: Convert Gen2 Stout, Porter, Silk to DM_SPI{,_FLASH}Marek Vasut2019-03-094-0/+8
| | | | | | | | | | | | | | | | | | | | | Enable DM_SPI and DM_SPI_FLASH in U-Boot on H2 Stout, M2W Porter and E3 Silk. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: dts: rmobile: Force 1-bit bus width on Gen2 QSPIMarek Vasut2019-03-097-0/+49
|/ / | | | | | | | | | | | | | | U-Boot currently uses Gen2 QSPI in 1-bit mode, enforce it until we can do better using the new SPI NOR framework. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch '2019-03-08-master-imports'Tom Rini2019-03-089-14/+77
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | - Assorted minor fixes: - ARM: qemu-arm: enable USB boot in distro boot with UEFI - image: fdt: handle coalesced reserve region - cmd: thordown: Fix spelling of download. - fdt: Fix FIT header verification in mkimage and conduct same checks as bootm - test: Update test-imagetools.sh to match new syntax
| * | ARM: qemu-arm: enable USB boot in distro boot with UEFIAKASHI Takahiro2019-03-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | With this patch which adds a removable USB mass storage to a list of bootable devices, USB boot is supported in distro boot if UEFI is configured. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
| * | image: fdt: handle coalesced reserve regionPatrick Delaunay2019-03-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle in boot_fdt_reserve_region any return value > 0 of lmb_reserve() function; it occurs when coalesced region are found: adjacent reserved region are merged. This patch avoid the error trace: ERROR: reserving fdt memory region failed.. when reserved region are merged (return value = 1). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | cmd: thordown: Fix spelling of download.Vagrant Cascadian2019-03-081-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
| * | fdt: Fix FIT header verification in mkimage and conduct same checks as bootmJordan Hand2019-03-085-3/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIT header verification in mkimage was treating a return code as a boolean, which meant that failures in validating the fit were seen as successes. Additionally, mkimage was checking all formats to find a header which passes validation, rather than using the image type specified to mkimage. checkpatch.pl checks for lines ending with '(' and alignment matching open parentheses are ignored to keep with existing coding style. Signed-off-by: Jordan Hand <jorhand@microsoft.com>
| * | test: Update test-imagetools.sh to match new syntaxMartyn Welch2019-03-081-8/+8
|/ / | | | | | | | | | | | | | | | | | | | | | | The syntax of dumpimage was simplified in commit 12b831879a76 ("tools: dumpimage: Simplify arguments"), but the test (test/image/test-imagetools.sh) was not updated and is now failing. Update the test to use the new syntax. Reported-by: Vagrant Cascadian <vagrant@debian.org> Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Tested-by: Vagrant Cascadian <vagrant@debian.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2019-03-083-57/+129
|\ \ | |/ |/| | | | | | | | | | | This pull request contains bugfixes for rcar_i2c, rcar_ii2c and i2c_cdns driver. Also the commit "i2c: rcar_i2c: Add Gen3 SoC support" from Marek is a bugfix for arm64 builds, as discussed with Marek on list.
| * i2c: rcar_i2c: Move FSDA check to rcar_i2c_recoverIsmael Luceno Cortes2019-03-081-5/+6
| | | | | | | | | | | | | | Cosmetic change. Any call to the recover function would need to do the same check afterwards, so it's sensible to make it part of the function. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
| * i2c: rcar_i2c: Set the slave address from rcar_i2c_xferIsmael Luceno Cortes2019-03-081-9/+5
| | | | | | | | | | | | | | | | | | It needs to be done for both reads and writes, so do it at rcar_i2c_xfer to avoid duplication. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Don't mask errors with EREMOTEIO at rcar_i2c_xferIsmael Luceno Cortes2019-03-081-1/+1
| | | | | | | | | | | | | | | | | | | | Fix rcar_i2c_xfer return value, previously it was always returning -EREMOTEIO when dealing with errors from calls to the read/write functions. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Fix sending of slave addressesIsmael Luceno Cortes2019-03-081-1/+3
| | | | | | | | | | | | | | | | | | Do the reset before clearing the MSR, otherwise it may result in a read or write operation instead if the start condition is repeated. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Add comments about registers & valuesIsmael Luceno Cortes2019-03-081-21/+26
| | | | | | | | | | | | | | | | | | Document the meaning of macros related to registers and values to be written to them. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * i2c: rcar_i2c: Setup SCL/SDA delay at rcar_i2c_set_speedIsmael Luceno Cortes2019-03-081-3/+6
| | | | | | | | | | | | | | | | | | Setting up the delay only needs to be done once; move it to rcar_i2c_set_speed so it's done at initialization time. Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de>
View Lorry Controller Status