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* Removed unused references to CONFIG_SERIALxAdam Ford2018-08-1736-43/+6
| | | | | | | | | After creating CONS_INDEX and migrating a bunch of boards to it, there are a bunch of defined references to CONFIG_SERIALx which are not referenced in any C code or #ifdef, so they can now be removed Signed-off-by: Adam Ford <aford173@gmail.com>
* Convert CONFIG_TWL4030_LED et al to KconfigAdam Ford2018-08-1727-16/+23
| | | | | | | | | | | This converts the following to Kconfig: CONFIG_TWL4030_LED CONFIG_TWL4030_INPUT This also removes dead references to: CONFIG_TWL4030_KEYPAD Signed-off-by: Adam Ford <aford173@gmail.com>
* Convert CONFIG_VIDEO_OMAP3 to KconfigAdam Ford2018-08-1712-6/+11
| | | | | | | This converts the following to Kconfig: CONFIG_VIDEO_OMAP3 Signed-off-by: Adam Ford <aford173@gmail.com>
* Convert CONFIG_MISC_INIT_R to KconfigAdam Ford2018-08-17447-235/+326
| | | | | | | | | This converts the following to Kconfig: CONFIG_MISC_INIT_R Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Update the defaults logic slightly] Signed-off-by: Tom Rini <trini@konsulko.com>
* Migrate bootlimit to KconfigAlex Kiernan2018-08-1737-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Migrate boards which set bootlimit in the environment to Kconfig. We exclude gurnard_defconfig which includes a bootlimit=, but doesn't set CONFIG_BOOTCOUNT_LIMIT, so we'd fail to include a bootlimit setting if we migrated it. display5_defconfig and display5_factory_defconfig share a SYS_CONFIG_NAME, but only display5_defconfig enables CONFIG_BOOTCOUNT_LIMIT, so we fail to set bootlimit= in display5_factory_defconfig. This is okay because the display5_factory_defconfig doesn't need to have it set, as it is only meant to prepare the board in the factory. Environment changes for all modified configs as seen from buildman: boards.cfg is up to date. Nothing to do. Summary of 3 commits for 32 boards (8 threads, 1 job per thread) 01: Merge git://git.denx.de/u-boot-x86 arm: + draco etamin rastaban pxm2 display5 thuban rut 02: Add BOOTCOUNT_BOOTLIMIT to set reboot limit 03: Migrate bootlimit to Kconfig - display5_factory: bootlimit=3 Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* Add BOOTCOUNT_BOOTLIMIT to set reboot limitAlex Kiernan2018-08-172-0/+11
| | | | | | Add ability to set environment bootlimit from Kconfig Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
* Convert CONFIG_MII et al to KconfigAdam Ford2018-08-17882-630/+714
| | | | | | | | | | This converts the following to Kconfig: CONFIG_MII CONFIG_DRIVER_TI_EMAC Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* dts: Fix typo in OF_LIVE Kconfig helpMichal Simek2018-08-171-1/+1
| | | | | | Fix typo in Kconfig description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* kconfig: fix typo 'parition'Simon Goldschmidt2018-08-172-2/+2
| | | | | | | | Replaced misspelled words "parition"/"paritioning" (missing 't') in two Kconfig files by correct words "partition"/"partitioning" Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2018-08-175-1/+202
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| * ARM: rmobile: Enable USB PHY on Gen2Marek Vasut2018-08-141-0/+2
| | | | | | | | | | | | | | | | Enable support for USB PHY on the R-Car Gen2. This allows for both of the USB host ports to be used on such boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * phy: rcar: Add R-Car Gen2 PHY driverMarek Vasut2018-08-143-0/+199
| | | | | | | | | | | | | | | | Add a PHY driver for the R-Car Gen2 which allows configuring the mux connected to the EHCI controllers and USBHS controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * phy: Fix off-by-one error when parsing DT PHY bindingsMarek Vasut2018-08-141-1/+1
| | | | | | | | | | | | | | | | | | The code fails to copy the last PHY phandle argument, so it is missing from the adjusted phandle args and the consumer cannot use it to determine what the PHY should do. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2018-08-1735-627/+800
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| * | arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit maskLey Foon Tan2018-08-151-3/+3
| | | | | | | | | | | | | | | | | | Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: clk: Convert to clock frameworkMarek Vasut2018-08-132-218/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use clock framework functions to fetch clock information now that there is a clock driver for Arria10, instead of custom coded register parsing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | mmc: socfpga: Add clock framework supportMarek Vasut2018-08-131-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for fetching the clock frequency both using the legacy method in case clock framework is disabled as well as via the clock framework if it is enabled. This allows for migration to the clock framework on platforms which supports it while not breaking legacy platforms. That said, the legacy method must be removed eventually. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | clk: socfpga: Add initial Arria10 clock driverMarek Vasut2018-08-133-0/+371
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodesMarek Vasut2018-08-133-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pre-reloc DT markers to clock nodes needed in SPL and early U-Boot stages. This is required to let the Arria10 clock driver start early and provide clock information for UART and SDMMC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: clk: Drop unused variables on Arria10Marek Vasut2018-08-131-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variables removed in this patch are never used, they are only ever assigned and then waste precious memory. Drop both the assignment and the variables. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 onlyMarek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L4SP and MMC clock precalculation is specific to Gen5, it is not needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper clock driver for Gen5, at which point this will go away completely. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: clk: Obtain handoff base clock via DMMarek Vasut2018-08-132-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Enable DM ethernet on A10Marek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable DM ethernet framework on Arria10, so that the designware GMAC can be probed from DT as it should be. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Remove adhoc ethernet reset and configurationMarek Vasut2018-08-133-50/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove ad-hoc ethernet syscon registers configuration and reset support. Reset is now handled by the reset framework and the syscon registers are set in the dwmac_socfpga.c driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Zap unused reset codeMarek Vasut2018-08-132-126/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove code from the reset manager that is never called. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | net: designware: socfpga: Add Arria10 extrasMarek Vasut2018-08-133-0/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add wrapper around the designware MAC driver to handle the SoCFPGA specific configuration bits. On Arria10, this is configuration of syscon phy_intf. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * | ARM: socfpga: Zap all the UART handling complexityMarek Vasut2018-08-135-149/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UART reset handling is now done via reset framework using the SoCFPGA reset driver. The UART console assignment is done using the DM and console framework. Nuke all this comlexity, since it is just duplicating the same functionality, badly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * | ARM: socfpga: Enable DM I2C framework on A10Marek Vasut2018-08-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the DM I2C framework on Arria10, so that the DM capable Designware I2C driver can handle the reset via DM reset framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Enable DM reset framework on A10Marek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Add i2c alias to A10 SoCDKMarek Vasut2018-08-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign the I2C bus a bus number. Add the missing alias. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Add missing I2C resetsMarek Vasut2018-08-131-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2Cx resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Fix Arria10 GMAC resetsMarek Vasut2018-08-131-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs to work and add GMAC2 reset and OCP resets which were missing altogether. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Add missing UART resetsMarek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UART0 and UART1 resets are missing from DT, so the reset manager cannot control them. Add the missing DT reset entries. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: dts: socfpga: Flag reset manager on A10 as pre-relocMarek Vasut2018-08-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Altera reset manager block must be available very early on, since it controls ie. UART resets. Flag it as pre-reloc. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
| * | ARM: socfpga: Register the FPGA on A10 in SPL againMarek Vasut2018-08-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The restructuring of the SPL dropped registration of the FPGA in SPL, readd it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Fixes: c859f2a77d98 ("arm: socfpga: Restructure the SPL file")
| * | arm: socfpga: gen5: combine some init code for SPL and U-BootSimon Goldschmidt2018-08-133-39/+22
| | | | | | | | | | | | | | | | | | | | | | | | Some of the code for low level system initialization in SPL's board_init_f() and U-Boot's arch_early_init_r() is the same, so let's combine it into a single function called from both. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: socfpga: fix device trees to work with DM serialSimon Goldschmidt2018-08-1311-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | Device trees need to have the serial console device available before relocation and require a stdout-path in chosen at least for SPL to have a console. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: socfpga: cyclone5: handle debug uartSimon Goldschmidt2018-08-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_DEBUG_UART is enabled, correctly initialize the debug uart before console is initialized to debug early boot problems in SPL. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: socfpga: spl_gen5: clean up malloc_base assignmentSimon Goldschmidt2018-08-131-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In spl_gen5's board_init_f(), gd->malloc_base is manually assigned at the end of the function to point to sdram. This code is outdated as by now, the heap is switched to sdram by the common function spl_relocate_stack_gd() if the appropriate defines are set. As it was, the value assigned manually was directly overwritten by this common code, so remove the manual assignment. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | arm: socfpga: fix SPL on gen5 after moving to DM serialSimon Goldschmidt2018-08-131-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were NULL pointers dereferenced because DM was used too early without correct initialization: - malloc_simple returned NULL when called from preloader_console_init() because gd->malloc_limit was 0 - uclass_add dereferenced gd->uclass_root members which were NULL because dm_init (or one of its relatives) has not been called. All this is fixed by calling spl_early_init before calling preloader_console_init. This fixes commit 73172753f4f3 ("ARM: socfpga: Convert to DM serial") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | configs: Migrate CONFIG_NR_DRAM_BANKSTom Rini2018-08-161017-334/+746
| | | | | | | | | | | | | | | | | | | | | | We have the following cases: - CONFIG_NR_DRAM_BANKS was defined, migrate normally - CONFIG_NR_DRAM_BANKS_MAX was defined and then used for CONFIG_NR_DRAM_BANKS after a check, just migrate it over now. - CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 + 2), set this to 8. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Kconfig: Migrate CONFIG_NR_DRAM_BANKSRamon Fried2018-08-161-0/+6
| | | | | | | | | | | | Move CONFIG_NR_DRAM_BANKS from headers to Kconfig. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* | fdt_support: Use CONFIG_NR_DRAM_BANKS if necessaryRamon Fried2018-08-161-0/+4
| | | | | | | | | | | | | | | | If CONFIG_NR_DRAM_BANKS is bigger than the default value (4) define MEMORY_BANKS_MAX as CONFIG_NR_DRAM_BANKS. Fixes: 2a1f4f1758b5 ("Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS if defined"") Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
* | CONFIG_SYS_GENERIC_BOARD: Finish migrationTom Rini2018-08-165-28/+0
| | | | | | | | | | | | | | | | While we have long since migrated to CONFIG_SYS_GENERIC_BOARD being enabled, we had just a few places left that still referenced or defined it. Update. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Prepare v2018.09-rc2v2018.09-rc2Tom Rini2018-08-131-1/+1
| | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* | configs: Resync with savedefconfigTom Rini2018-08-133-23/+1
| | | | | | | | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* | MAINTAINERS: Update STM32MP fragmentsPatrice Chotard2018-08-131-0/+10
| | | | | | | | | | | | | | Add new drivers Add Christophe Kerello and myself as maintainers Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: dts: stm32f4: Fix DT dtc warningsPatrick Delaunay2018-08-133-6/+0
| | | | | | | | | | | | | | | | | | | | | | This patch fix the following warnings for for stm32f429 evaluation and discovery boards: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: dts: stm32mp157: Add ADC DT nodePatrice Chotard2018-08-131-0/+32
| | | | | | | | | | | | | | | | Add ADC device tree node. This allows to get analog conversions on stm32mp157. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* | ARM: dts: stm32: remove cd-inverted for stm32f746-discoPatrice Chotard2018-08-131-2/+2
| | | | | | | | | | | | | | | | As cd-inverted property is no more used by arm_pl180_mmci driver, remove it. Update cd-gpios active level accordingly. Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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