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* Convert CONFIG_PCIE1 et al to KconfigTom Rini2022-07-05171-70/+512
| | | | | | | | | | | This converts the following to Kconfig: CONFIG_PCIE1 CONFIG_PCIE2 CONFIG_PCIE3 CONFIG_PCIE4 CONFIG_PCI1 Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_LAYERSCAPE_NS_ACCESS to KconfigTom Rini2022-07-0587-140/+200
| | | | | | | This converts the following to Kconfig: CONFIG_LAYERSCAPE_NS_ACCESS Signed-off-by: Tom Rini <trini@konsulko.com>
* lcd: Remove legacy CONFIG_FB_ADDR codeTom Rini2022-07-055-22/+0
| | | | | | | No platforms set both CONFIG_LCD and CONFIG_FB_ADDR at this time, drop this legacy code. Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_FSL_FIXED_MMC_LOCATION et al to KconfigTom Rini2022-07-0524-19/+33
| | | | | | | | This converts the following to Kconfig: CONFIG_FSL_FIXED_MMC_LOCATION CONFIG_ESDHC_HC_BLK_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
* powerpc: Clean up CHAIN_OF_TRUST related optionsTom Rini2022-07-058-89/+66
| | | | | | | | | | | | | | | | | As things stand currently, there is only one PowerPC platform that enables the options for CHAIN_OF_TRUST. From the board header files, remove a number of never-set options. Remove board specific values from arch/powerpc/include/asm/fsl_secure_boot.h as well. Rework include/config_fsl_chain_trust.h to not abuse the CONFIG namespace for constructing CHAIN_BOOT_CMD. Migrate all of the configurable addresses to Kconfig. If any platforms are re-introduced with secure boot support, everything required should still be here, but now in Kconfig, or requires migration of an option to Kconfig. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* nxp: config_fsl_chain_trust.h: Clean up and remove unused portionsTom Rini2022-07-052-96/+0
| | | | | | | | | | | | The way that secure boot is implemented today on NXP ARM platforms does not reuse the elements found in include/config_fsl_chain_trust.h to construct CONFIG_SECBOOT but instead board header files have their environment setup as needed and then fsl_setenv_chain_of_trust() will set secureboot in the environment. Remove a large number of unused defines here. Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* fsl_validate: Migrate SPL_UBOOT_KEY_HASH to KconfigTom Rini2022-07-054-24/+12
| | | | | | | | | | | Move setting of SPL_UBOOT_KEY_HASH to a non-NULL value to Kconfig. As part of this, change fsl_secboot_validate(...) to check that it is passed a non-empty string, rather than non-NULL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Cc: Kshitiz Varshney <kshitiz.varshney@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* arch/Kconfig.nxp: Re-organize slightlyTom Rini2022-07-055-74/+24
| | | | | | | | | | Make all of the CHAIN_OF_TRUST options be under a single menu and add a comment for the rest, so the resulting config file reads more clearly. Remove duplicate CHAIN_OF_TRUST options from board/congatec/common/Kconfig. Remove duplicate NXP_ESBC config questions and move to arch/Kconfig.nxp. Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_FSL_SFP_BE et al to KconfigTom Rini2022-07-058-55/+37
| | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_KEY_REVOCATION CONFIG_SYS_FSL_SFP_BE CONFIG_SYS_FSL_SFP_LE CONFIG_SYS_FSL_SFP_VER_3_0 CONFIG_SYS_FSL_SFP_VER_3_2 CONFIG_SYS_FSL_SFP_VER_3_4 CONFIG_SYS_FSL_SRK_LE This partly means making sure to enable SYS_FSL_ERRATUM_A007186 only for when CHAIN_OF_TRUST is enabled. Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_FSL_SEC_MON et al to KconfigTom Rini2022-07-0524-23/+31
| | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_FSL_SEC_MON CONFIG_SYS_FSL_SEC_MON_BE CONFIG_SYS_FSL_SEC_MON_LE Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_ESDHC_DETECT_QUIRK to KconfigTom Rini2022-07-0522-54/+41
| | | | | | | This converts the following to Kconfig: CONFIG_ESDHC_DETECT_QUIRK Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_ESBC_HDR_LS et al to KconfigTom Rini2022-07-054-20/+14
| | | | | | | | This converts the following to Kconfig: CONFIG_ESBC_HDR_LS CONFIG_ESBC_ADDR_64BIT Signed-off-by: Tom Rini <trini@konsulko.com>
* nxp: Rename board/freescale/common/Kconfig to arch/Kconfig.nxpTom Rini2022-07-052-1/+6
| | | | | | | | | | | Now that board/freescale/common/Kconfig is safe to be included once, globally, rename this to arch/Kconfig.nxp to better reflect that it contains options that are valid on multiple architectures and SoC families, and not specific to NXP reference platforms either. Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* nxp: Make board/freescale/common/Kconfig safe to include once in arch/KconfigTom Rini2022-07-0545-94/+14
| | | | | | | | | | The way that we use this file currently means that we have to guard it in every platform Kconfig. But it is also required in all NXP platforms, including non-reference platforms. Make all options in it have appropriate dependencies so that we can include it a single time under arch/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_HETROGENOUS_CLUSTERS et al to KconfigTom Rini2022-07-052-8/+34
| | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_HETROGENOUS_CLUSTERS CONFIG_SYS_MAPLE CONFIG_SYS_CPRI CONFIG_PPC_CLUSTER_START CONFIG_DSP_CLUSTER_START CONFIG_SYS_CPRI_CLK CONFIG_SYS_ULB_CLK CONFIG_SYS_ETVPE_CLK Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_EXTRA_CLOCK to KconfigTom Rini2022-07-052-1/+3
| | | | | | | This converts the following to Kconfig: CONFIG_EXTRA_CLOCK Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_DDR_RAW_TIMING to KconfigTom Rini2022-07-0555-18/+54
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_DDR_RAW_TIMING Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_SPD_BUS_NUM to KconfigTom Rini2022-07-0575-38/+52
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_SPD_BUS_NUM Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR to KconfigTom Rini2022-07-053-6/+5
| | | | | | | This converts the following to Kconfig: CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_USB_GADGET_DWC2_OTG_PHY to KconfigTom Rini2022-07-0511-8/+11
| | | | | | | This converts the following to Kconfig: CONFIG_USB_GADGET_DWC2_OTG_PHY Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_USE_ONENAND_BOARD_INIT to KconfigTom Rini2022-07-058-4/+7
| | | | | | | This converts the following to Kconfig: CONFIG_USE_ONENAND_BOARD_INIT Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SAMSUNG_ONENAND to KconfigTom Rini2022-07-057-3/+6
| | | | | | | | This converts the following to Kconfig: CONFIG_SAMSUNG_ONENAND Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* Rename CONFIG_PWM to CONFIG_PWM_S5P and move to KconfigTom Rini2022-07-058-11/+9
| | | | | | | | | | | We rename the S5P specific "CONFIG_PWM" to CONFIG_PWM_S5P and move it to Kconfig. Given the usage of CONFIG_PWM_NX, we have that select this new symbol. Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* smdkc100: Remove some unused optionsTom Rini2022-07-051-10/+0
| | | | | | | There are a few options we test and set and then never reference, remove them. Signed-off-by: Tom Rini <trini@konsulko.com>
* nxp: Cleanup some emulator related options.Tom Rini2022-07-053-8/+6
| | | | | | | | - Drop the emulator CONFIG test from include/configs/ls1088ardb.h - Migrate CONFIG_SYS_FSL_DDR_EMU to a select'able option in drivers/ddr/fsl/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* watchdog: designware: Make this depend on WDTTom Rini2022-07-054-25/+2
| | | | | | | | | | | | | | | | | | As this driver can dynamically determine the values set in CONFIG_DW_WDT_BASE when using WDT, so make this depend on WDT rather than migrate CONFIG_DW_WDT_BASE to Kconfig. Cc: Chee Tien Fong <tien.fong.chee@intel.com> Cc: Chin-Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinh.nguyen@intel.com> Cc: Holger Brunck <holger.brunck@hitachienergy.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Stefan Roese <sr@denx.de> Cc: hee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
* Convert CONFIG_ENABLE_36BIT_PHYS to KconfigTom Rini2022-07-0595-22/+84
| | | | | | | This converts the following to Kconfig: CONFIG_ENABLE_36BIT_PHYS Signed-off-by: Tom Rini <trini@konsulko.com>
* net: designware: Rename CONFIG_DW_GMAC_DEFAULT_DMA_PBL to GMAC_DEFAULT_DMA_PBLTom Rini2022-07-052-7/+3
| | | | | | | This value is always used at the default, rename it for now. This likely should come from the device tree if non-default, moving forward. Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_DW_ALTDESCRIPTOR to KconfigTom Rini2022-07-0514-20/+13
| | | | | | | This converts the following to Kconfig: CONFIG_DW_ALTDESCRIPTOR Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'fsl-qoriq-2022-7-3' of ↵Tom Rini2022-07-048-67/+49
|\ | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next Several patches from Pali - fsl_elbc detection fix - sort p2020 dts node, drop duplicated node - p1_p2_rdb_pc board cleanup - simplify mpc85xx _start_cont jumping code
| * powerpc: mpc85xx: Simplify jump to _start_cont in flash codePali Rohár2022-07-031-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After more patches code for jumping to _start_cont symbol in flash memory involved to code with useless mathematical operations. Currently it does: r3 := CONFIG_SYS_MONITOR_BASE + ABS(_start_cont) - CONFIG_SYS_MONITOR_BASE jump to r3 Which is equivalent of just: r3 := ABS(_start_cont) jump to r3 The purpose of that code is just to jump to _start_code symbol, independently of program counter. So branch must be done to absolute address. Trying to write: ba _start_cont just cause linker error: LD u-boot powerpc-linux-gnuspe-ld.bfd: arch/powerpc/cpu/mpc85xx/start.o: in function `switch_as': (.bootpg+0x4b8): relocation truncated to fit: R_PPC_ADDR24 against symbol `_start_cont' defined in .text section in arch/powerpc/cpu/mpc85xx/start.o make: *** [Makefile:1801: u-boot] Error 1 Probably by the fact that absolute address cannot be expressed by 24-bits. So write the code via mtlr+blr pattern as it was before and load general purpose register with absolute address of the symbol: lis r3,_start_cont@h ori r3,r3,_start_cont@l mtlr r3 blr Seems that gcc and gnu ld linker support symbol@h and symbol@l syntax like number@h and number@l without any problem. And disassembling of compiler u-boot binary proved that lis+ori instructions are called with numbers which represent halves of absolute address of _start_cont symbol. Signed-off-by: Pali Rohár <pali@kernel.org>
| * board: freescale: p1_p2_rdb_pc: Remove mapping for TDM-PMC cardPali Rohár2022-07-034-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From whole P1/P2 family of RDB boards is TDM-PMC card (PCI Mezzanine Card, Freescale PQ-MDS-T1) available only on P1021RDB and P1025RDB boards. So address mapping for TDM-PMC card on LBC should not be enabled on any other P1/P2 RDB board as there is no device at that TDM-PMC address. Support for P1021RDB and P1025RDB boards was already removed from mainline U-Boot in commits 6d1dd76afe85 ("board/freescale: Remove P1021RDB board support") and d521cece5adb ("board/freescale: Remove P1025RDB board support"). So do not enable TDM-PMC address mapping on remaining P1/P2 RDB boards and remove all macros related to TDM-PMC address mappings. Signed-off-by: Pali Rohár <pali@kernel.org>
| * board: freescale: p1_p2_rdb_pc: Allow to compile without __SW_BOOT_SD macroPali Rohár2022-07-031-1/+4
| | | | | | | | | | | | | | Add #ifdef guard for __SW_BOOT_SD macro like there are guards for all other __SW_BOOT_* macros. Signed-off-by: Pali Rohár <pali@kernel.org>
| * board: freescale: p1_p2_rdb_pc: Allow to compile without BOARD_NAMEPali Rohár2022-07-031-1/+5
| | | | | | | | Signed-off-by: Pali Rohár <pali@kernel.org>
| * powerpc: dts: p2020: Remove duplicate pic@40000 nodePali Rohár2022-07-031-12/+0
| | | | | | | | | | | | | | | | | | | | DT node pic@40000 is defined explicitly in p2020-post.dtsi file and also transitionally via include file pq3-mpic.dtsi. Remove duplicate definition from p2020-post.dtsi. No change in final DTB file. Signed-off-by: Pali Rohár <pali@kernel.org>
| * powerpc: dts: p2020: Sort DT nodes by their addressesPali Rohár2022-07-031-44/+45
| | | | | | | | | | | | No functional change. Signed-off-by: Pali Rohár <pali@kernel.org>
| * mtd: rawnand: fsl_elbc: Fix detection when nand_scan_ident() has not ↵Pali Rohár2022-07-031-1/+5
|/ | | | | | | | | | | | | | | | selected ecc.mode ecc.mode is set to 0 (aliased to NAND_ECC_NONE) either when function nand_scan_ident() has not selected ecc.mode or when it selected it to none ecc mode. Distinguish between these two states by checking of node property "nand-ecc-mode" which function nand_scan_ident() uses for filling ecc.mode. This change fixes usage of none ecc mode if it is specified in DTS file. Fixes: c9ea9019c5aa ("mtd: rawnand: fsl_elbc: Use ECC configuration from device tree") Signed-off-by: Pali Rohár <pali@kernel.org>
* Merge tag 'u-boot-at91-2022.10-a' of ↵Tom Rini2022-06-3031-88/+121
|\ | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-at91 into next First set of u-boot-at91 features for the 2022.10 cycle: This feature set includes mostly fixes and alignments: DT alignment with Linux for sama7g5, removal of invalid eeprom compatibles, removal of extra debug_uart_init calls for all at91 boards, support for pio4 driver pioE bank, and other minor fixes and enhancements for sam9x60 and sama5d2_icp boards.
| * gpio: atmel_pio4: add support for PIO_PORTEMihai Sain2022-06-302-0/+6
| | | | | | | | | | | | Add support for gpio PORT E, which is available on e.g. sama7g5 SoC. Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
| * board: atmel: remove calls to debug_uart_initEugen Hristev2022-06-2819-60/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since 0dba45864b ("arm: Init the debug UART") , the debug_uart_init is now called from crt.S It's no longer required to call it from the board file. With the current code, the banned <debug_uart> is printed twice: <debug_uart> <debug_uart> U-Boot 2022.07-rc4-00089-gee3d158fa8 (Jun 08 2022 - 17:39:29 +0300) Remove all calls from board_early_init_f . Suggested-by: Balamanikandan Gunasundar <Balamanikandan.Gunasundar@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * ARM: dts: at91: sam9x60ek: fix eeprom compatibleEugen Hristev2022-06-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | The memory on this board is microchip 24aa025e48 which is compatible with at24c02 with a page size of 16. Fix the compatible accordingly. Reported-by: Sergiu Moga <sergiu.moga@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Tested-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
| * misc: i2c_eeprom: remove 24aa02e48Eugen Hristev2022-06-281-8/+0
| | | | | | | | | | | | | | | | | | | | This compatible does not exist in the bindings. All occurences in DT have been replaced by at24c02 which is equivalent. Fixes: 7264066707 ("misc: i2c_eeprom: Add compatible for 24AA02E48") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Heiko Schocher <hs@denx.de>
| * ARM: dts: at91: replace microchip, 24aa02e48 with atmel, at24c02Eugen Hristev2022-06-283-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | microchip,24aa025e48 does not exist in the bindings of this driver. It can be replaced with atmel,at24c02 which is a standard compatible and the memory is compatible with this one, depending on the page size. microchip 24aa02e48 has a page size of 8, while 24aa025e48 has a page size of 16 bytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Reviewed-by: Heiko Schocher <hs@denx.de>
| * ARM: dts: at91: sama7g5/sama7g5ek: sync with kernel at91 5.19Eugen Hristev2022-06-282-12/+55
| | | | | | | | | | | | Sync with at91 maintainer tree for-5.19 branch. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * dt-bindings: sound: add microchip,pdmc.hEugen Hristev2022-06-281-0/+13
| | | | | | | | | | | | | | | | Include microchip,pdmc.h from Linux. This file includes required defines for DT successful build. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * configs: at91: sama5d2_icp: enable QSPI and SF commandSergiu Moga2022-06-281-0/+13
| | | | | | | | | | | | | | | | | | Add the configurations required for enabling QSPI and the SF command to allow changes to be made dynamically to serial flash devices from the command line interface. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * configs: at91: sam9x60ek: enable QSPI and SF commandSergiu Moga2022-06-282-0/+26
| | | | | | | | | | | | | | | | | | Add the configurations required for enabling QSPI and the SF command to allow changes to be made dynamically to serial flash devices from the command line interface. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * ARM: dts: sam9x60: fix compatible for qspi child nodeSergiu Moga2022-06-281-1/+1
| | | | | | | | | | | | | | | | | | Change the compatible of the qspi child node to `jedec,spi-nor` so that it can be properly found when probing the bus. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
* | Merge tag 'versal-qspi-for-v2022.10' of ↵Tom Rini2022-06-3011-155/+547
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Versal QSPI/OSPI changes for v2022.10 - Add new flash types - Add cadence ospi driver for Xilinx Versal
| * | spi: cadence-qspi: Fix programming ospi flash speedT Karthik Reddy2022-06-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the requested flash speed is 0, the baudrate division for the requested speed causing drop in the performance. So set the ospi flash to operate at max frequency when requested speed is zero. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220512100535.16364-6-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
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