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| * soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driverT Karthik Reddy2021-08-268-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | soc_xilinx_zynqmp driver allows identification of family & revision of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP. Add this config to xilinx_zynqmp_virt_defconfig file. Probe this driver using platdata U_BOOT_DEVICE structure which is specified in mach-zynqmp/cpu.c. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * fdt_support: Add kernel-doc for fdt_fixup_memory_banks()Michal Simek2021-08-261-0/+18
| | | | | | | | | | | | | | | | | | | | | | Add kernel-doc description for fdt_fixup_memory_banks() because it is implemented in one specific way and this information should be available for others to decide if their SoC conforms to it. If you don't want U-Boot to update your memory DT layout please disable CONFIG_ARCH_FIXUP_FDT_MEMORY. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * xilinx: Disable ARCH_FIXUP_FDT_MEMORYMichal Simek2021-08-263-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on DT spec you can have one memory node which multiple ranges or multiple nodes. fdt_fixup_memory_banks() is not implemented in a correct way when multiple memory nodes are present because all ranges are put it to the first memory node found. And next memory nodes are kept in DT which ends up in the same range specification in the same DT. Here is what it is happening. Origin DT. memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; memory@800000000 { device_type = "memory"; reg = <0x8 0x00000000 0x0 0x80000000>; }; After fdt_fixup_memory_banks() memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; memory@800000000 { device_type = "memory"; reg = <0x8 0x00000000 0x0 0x80000000>; }; As is visible memory@0 node got second range but there is still memory@800000000 node present and 2G range is listed twice. The solution can't be that second node is removed because it can be referenced already that's why it is better for us to disable this option for now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Enable smcc and nor for zc770-xm012Michal Simek2021-08-261-0/+9
| | | | | | | | | | | | Enable cfi flash on zc770-xm012 configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Wire single qspi on couple of boardsMichal Simek2021-08-264-0/+32
| | | | | | | | | | | | Single configuration is working fine and no issue to enable it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM: zynq: Replace 'io-standard' with 'power-source' propertySai Krishna Potthuri2021-08-262-20/+20
| | | | | | | | | | | | | | | | Replace 'io-standard' property with 'power-source' property in all zynq dts files to be in sync with Zynq Pinctrl driver. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)Raju Kumar Pothuraju2021-08-264-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing "jedec, spi-nor" compatible string for QSPI flash node. Spi-nor framework uses this compatibility string to probe & initialize flash. With missing compatibility string we are observing below error: Zynq> sf probe 0 0 0 jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes: 00, 00, 00 Failed to initialize SPI flash at 0:0 (error -2) Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Update comment style sm-k26Michal Simek2021-08-261-1/+1
| | | | | | | | | | | | Trivial style patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Fix header alignment on kv260 boardsMichal Simek2021-08-262-8/+8
| | | | | | | | | | | | Fix header alignment. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Fix node name for ds35/36 ledsMichal Simek2021-08-261-2/+2
| | | | | | | | | | | | By dt-binding specs led nodes should have -led suffix that's why add it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: Initialize usb and scsi via prebootMichal Simek2021-08-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on thread https://lists.denx.de/pipermail/u-boot/2021-June/451828.html especially "Overall we have a deficiency in the UEFI implementation in that we cannot deal with block devices added or removed after initialization." there is a need to deal with removable media as usb/scsi/sata. That's why bridge this gap in EFI implementation by resetting usb and scsi resets to get all disks before efi_init_obj_list() is called. In our standard boot flow, where we use distro boot, order is fixed as "jtag mmc0 mmc1 qspi0 nand0 usb0 usb1 scsi0 pxe dhcp" with prioritizing boot device added by commit 2882b39d564b ("arm64: zynqmp: Setup the first boot_target at run time"). When device has ESP partition all devices should be detected because then efi_disk_register() in efi_init_obj_list() is called only once. The first such a device is sd/emmc(mmc0/mmc1) and then disks on usb/sata are not handled at all. The commit 6bb577dbb30f ("arm64: zynqmp: Disable EFI_CAPSULE_ON_DISK_EARLY") also pointed out on this issue but detection of removable media wasn't solved that's why do it now via preboot command. I have tested cases without usb and scsi and there is no problem with calling resets without devices itself. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * arm64: zynqmp: Disable WDT_CDNS driver by defaultMichal Simek2021-08-261-1/+0
| | | | | | | | | | | | | | | | | | Do not enable watchdog driver in default zynqmp configuration. The reason is that not all distributions are handling watchdog properly and then expires and system resets. If someone needs watchdog in their design please enable it by hand. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: zynq_sdhci: Use set_control_reg from sdhci.cAshok Reddy Soma2021-08-261-20/+1
| | | | | | | | | | | | | | | | | | Since set_control_reg is available in sdhci.c, use it and remove arasan_sdhci_set_control_reg(). Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: zynq_sdhci: Wait till sd card detect state is stableT Karthik Reddy2021-08-261-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per SD spec when SD host controller is reset, it takes 1000msec to detect the card state. In case, if we enable the sd bus voltage & card detect state is not stable, then host controller will disable the sd bus voltage. In case of warm/subsystem reboot, due to unstable card detect state host controller is disabling the sd bus voltage to sd card causing sd card timeout error. So we wait for a maximum of 1000msec to get the card detect state stable before we enable the sd bus voltage. This current fix is workaround for now, this needs to be analysed further. Zynqmp platform should behave the same as Versal, but we did not encounter this issue as of now. So we are fixing it for Versal only. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: zynq_sdhci: Move setting tapdelay code to driverAshok Reddy Soma2021-08-264-152/+107
| | | | | | | | | | | | | | | | | | | | | | | | Move tapdelay function calls to zynq_sdhci.c and make them static inline. zynqmp_tap_delay.h has function prototypes for the functions defined in tap_delays.c, which will not be needed anymore. Remove tap_delays.c and zynqmp_tap_delay.h files. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: zynq_sdhci: Add xilinx_pm_request() method to set tapdelaysAshok Reddy Soma2021-08-263-87/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently xilinx sdhci driver is using zynqmp_mmio_write() to set tapdelay values and DLL resets. Continue to use this for SPL and mini U-Boot where U-Boot will be executed at EL3 level. Use firmware call xilinx_pm_request() using appropriate arguments to set input/output tapdelays and also for DLL resets in regular flow(EL2). Host driver should explicitly request DLL reset before ITAP (assert DLL) and after OTAP (release DLL) to avoid issues in some cases. Also handle error return where possible. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * zynqmp_firmware: Add zynqmp firmware related enumsT Karthik Reddy2021-08-061-0/+127
| | | | | | | | | | | | | | | | Add enums for pm node id's, pm ioctl id's, tapdelay types, dll reset types Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: sdhci: Change prototype of set_delay to return errorsAshok Reddy Soma2021-08-062-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | set_delay() has return type as void. If there are any errors while setting tapdelay's it won't be able to return them. Change the prototype of set_delay() in sdhci_ops structure and return the errors from wherever it is called. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * mmc: zynq_sdhci: Return errors from arasan_sdhci_set_tapdelayAshok Reddy Soma2021-08-061-5/+18
| | | | | | | | | | | | | | | | | | | | | | Change return type of arasan_sdhci_set_tapdelay() to int, to facilitate returning errors. Get return values from input and output set clock phase functions inside arasan_sdhci_set_tapdelay() and return those errors. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * reset: zynqmp: Add reset controller for ZynqMP SoCMichal Simek2021-08-065-0/+242
| | | | | | | | | | | | | | | | | | | | Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: Enable CMD_RTC command with Zynqmp RTC driverMichal Simek2021-08-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Enable RTC command to be able to check available. And also enable ZynqMP RTC driver to be possible to use by default. Here is the list when both drivers are enabled: ZynqMP> rtc list RTC #0 - rtc_emul RTC #1 - rtc@ffa60000 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * rtc: zynqmp: Add support for ZynqMP RTCMichal Simek2021-08-064-0/+167
| | | | | | | | | | | | | | | | The whole driver logic is taken from Linux kernel but only set/get/reset functions are implemented. When device is power off RTC is power out of battery. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * cmd: date: rtc: Update command to read the first RTC with seq 0Michal Simek2021-08-061-3/+6
| | | | | | | | | | | | | | | | | | | | | | RTCs are using sequence number defined in aliases node. Date command with DM_RTC enabled is looking for the first RTC with index 0. But when RTC_EMULATION is enabled it gets likely most of the time index 0 even when system has rtc0 device via aliases node and gets sequence number 0. That's why extend the code to look for sequence 0 number first. If this fails continue to use existing device with index 0. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * dm: rtc: uclass: Add flag to control sequence numberingMichal Simek2021-08-061-0/+1
| | | | | | | | | | | | | | | | | | RTCs are using aliases for sequences. That's why enable DM_UC_FLAG_SEQ_ALIAS for exact RTC indentification. The same flag is used by a lot of other uclasses like mmc, pci, serial, spi, timer, tpm, etc. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * firmware: xilinx: Use explicit values for all enum valuesMichal Simek2021-08-061-44/+49
| | | | | | | | | | | | | | | | | | | | Based on discussion at https://lore.kernel.org/r/20200318125003.GA2727094@kroah.com we got recommendation to use explicit values for all enum values. The patch is following this recommendation. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/daeb67ded45d8a8f6a96717d1fb9c84439dd2ae8.1612361627.git.michal.simek@xilinx.com
| * xilinx: zynqmp: Add support for runtime dfu_alt_info setupMichal Simek2021-08-062-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The main reason for this to be implemented is capsule update. Two memories are supported and tested which is MMC FAT based and QSPI based. For creating capsule these commands are used: ./tools/mkeficapsule --raw spl/boot.bin --index 1 capsule1.bin ./tools/mkeficapsule --raw u-boot.itb --index 2 capsule2.bin Then transfer to SD card where these commands run: load mmc 0 10000000 capsule1.bin efidebug capsule update -v 10000000 load mmc 0 10000000 capsule2.bin efidebug capsule update -v 10000000 Depends on the boot device used are binaries loaded to qspi or mmc fat partition. Also multiboot register is handled to make sure that the same location(id) is used as image which is upgraded. Two locations are used by purpose for SPL flow. If only boot.bin is used create only one capsule. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: Config non zero SYS_SPI_U_BOOT_OFFSMichal Simek2021-08-061-0/+1
| | | | | | | | | | | | | | | | This variable is pointing to offset is qspi where u-boot image is placed. In our case it is location of u-boot.itb file. Offset is the same as is used by Xilinx Zynq SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: use zynqmp_mmio_read() in multi_boot()Michal Simek2021-08-061-2/+5
| | | | | | | | | | | | | | | | When U-Boot runs in EL2 there is no access to csu_base registers that's why this has to be done via firmware interface to find out multi boot register value. Till now this function is called only from SPL in EL3. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: Change multi_boot() to return valueMichal Simek2021-08-061-4/+2
| | | | | | | | | | | | | | | | Change multi_boot() to return multiboot value and move print out of this function and let this function to be used by other functions without duplicating message. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * xilinx: zynqmp: Free allocated field for target variableMichal Simek2021-08-061-0/+1
| | | | | | | | | | | | | | When env_set() is called there is no need to allocate memory for variable which is already saved that's why free it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch 'next-socfpga' of https://github.com/tienfong/uboot_mainlineTom Rini2021-08-2543-90/+4467
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| * | arm: socfpga: Enable Intel N5X device buildSiew Chin Lim2021-08-255-6/+257
| | | | | | | | | | | | | | | | | | Add defconfig for N5X to support legacy, ATF and VAB boot flow. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | include: configs: Add Intel N5X device CONFIGsSiew Chin Lim2021-08-251-0/+45
| | | | | | | | | | | | | | | | | | Add CONFIGs for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: dts: Add base dtsi and devkit dts for Intel N5X deviceSiew Chin Lim2021-08-254-0/+377
| | | | | | | | | | | | | | | | | | | | | | | | Add device tree for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
| * | board: intel: Add socdk board support for Intel N5X deviceSiew Chin Lim2021-08-253-0/+21
| | | | | | | | | | | | | | | | | | Add N5X SoC devkit board. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: Add SPL for Intel N5X deviceSiew Chin Lim2021-08-251-0/+94
| | | | | | | | | | | | | | | | | | Add SPL for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee2021-08-256-2/+2386
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * | ddr: socfpga: Enable memory test on memory size less than 1GBTien Fong Chee2021-08-251-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | Minimum 1GB memory size is required in current memory test, so this patch improves the memory test for processing memory size less than 1GB, and the size in power of two. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * | arm: socfpga: Changed misc_s10.c to misc_soc64.cSiew Chin Lim2021-08-252-8/+8
| | | | | | | | | | | | | | | | | | | | | Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: Add clock manager for Intel N5X deviceSiew Chin Lim2021-08-253-0/+94
| | | | | | | | | | | | | | | | | | Add clock manager for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.hSiew Chin Lim2021-08-255-5/+1
| | | | | | | | | | | | | | | | | | | | | Move cm_get_mpu_clk_hz function declaration from individual device's clock manager header file to common clock_manager.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | drivers: clk: Add memory clock driver for Intel N5X deviceSiew Chin Lim2021-08-253-0/+221
| | | | | | | | | | | | | | | | | | | | | Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: Get clock manager base address for Intel N5X deviceSiew Chin Lim2021-08-251-0/+3
| | | | | | | | | | | | | | | | | | Add N5X clock manager to socfpga_get_managers_addr function. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | drivers: clk: Add clock driver for Intel N5X deviceSiew Chin Lim2021-08-254-1/+779
| | | | | | | | | | | | | | | | | | | | | Add clock manager driver for N5X. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: Add handoff data support for Intel N5X deviceTien Fong Chee2021-08-243-48/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | N5X support both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and N5X device. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * | arm: socfpga: Add base address for Intel N5X deviceSiew Chin Lim2021-08-241-1/+2
| | | | | | | | | | | | | | | | | | | | | Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.hSiew Chin Lim2021-08-242-5/+5
| | | | | | | | | | | | | | | | | | | | | Rename to common file name to used by all SOC64 devices and change "_S10_" to "_SOC64_" in base_addr_soc64.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux ↵Siew Chin Lim2021-08-243-10/+11
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | function Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when OS booted from FIT image for Stratix 10 and Agilex. This flow is common for all Intel SOC64 devices. U-Boot will update 'fdt_addr' environment value based on FIT image in board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr' environment value to retrieve the device tree node. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | Merge tag 'efi-2021-10-rc3' of ↵WIP/23Aug2021Tom Rini2021-08-2327-53/+100
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc3 Documentation: * Rename Freescale to NXP * Document structures used for the UEFI TCG2 protocol UEFI: * Device paths must use EfiBootServicesData
| * | efi_loader: use EfiBootServicesData for DP to textHeinrich Schuchardt2021-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | Memory allocated in the implementation of the EFI_DEVICE_PATH_TO_TEXT_PROTOCOL must be of type EfiBootServicesData. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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