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* power: Rename CONFIG_POWER_TPS65217 with CONFIG_PMIC_TPS65217Lukasz Majewski2022-04-0527-16/+42
| | | | | | | | | | | | | | | | Up till now the CONFIG_POWER_TPS65217 has been defined in several header files for am335x SoC. This patch renames it to CONFIG_PMIC_TPS65217, which better reflects the role of this IC circuit. Moreover, new CONFIG_PMIC_TPS65217 has been introduced in Kconfig to be used with boards, which both support DM_PMIC and DM_I2C. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> [trini: Migrate all other platforms as well] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch '2022-04-04-platform-updates'Tom Rini2022-04-0532-54/+621
|\ | | | | | | - Updates for exynos78x0 and TI K3 platforms
| * ram: k3-am654: Make VTT regulator optionalChristian Gmeiner2022-04-041-3/+2
| | | | | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * ram: k3-am654: Write all configuration valuesDominic Rath2022-04-041-0/+10
| | | | | | | | | | | | | | Makes it possible to use 16-bit DDR memory. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * configs: am64x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfigDave Gerlach2022-04-041-0/+1
| | | | | | | | | | | | | | Add CONFIG_NR_DRAM_BANKS from am64x_evm_a53_defconfig as this is needed to calculate the size of DDR that is available. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am64-ddr: Add ss_cfg reg entryDave Gerlach2022-04-041-2/+3
| | | | | | | | | | | | | | Add 'ss_cfg' memory region for memorycontroller node which is required to enable ECC. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * board: ti: am64x: Account for DDR size fixups if ECC is enabledDave Gerlach2022-04-041-2/+53
| | | | | | | | | | | | | | | | | | | | | | Call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled. A second fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-ddrss: Introduce ECC Functionality for full memory spaceDave Gerlach2022-04-042-0/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regsDave Gerlach2022-04-041-2/+3
| | | | | | | | | | | | | | | | | | The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * dt-bindings: memory-controller: Add information about ECC bindingsDave Gerlach2022-04-041-0/+8
| | | | | | | | | | | | | | Add DT binding documentation for enabling ECC in the DDR sub system present on AM64 device. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * board: ti: am64x: Use fdt functions for ram and bank initDave Gerlach2022-04-041-7/+12
| | | | | | | | | | | | | | | | | | Use the appropriate fdtdec_setup_mem_size_base and fdtdec_setup_bank_size calls in dram_init and dram_bank_init to pull these values from DT, where they are already available, instead of hardcoding them. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642-r5-evm: Mark memory with u-boot, dm-splDave Gerlach2022-04-041-0/+1
| | | | | | | | | | | | Mark the memory node with u-boot,dm-spl so we can use it from early SPL. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ARM: dts: k3-am642: Correct timer frequencyVignesh Raghavendra2022-04-042-2/+2
| | | | | | | | | | | | | | | | Timer0 runs at 200MHz,and the clock-frequency defined in DT is incorrect. Fix it. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-By: Nishanth Menon <nm@ti.com>
| * configs: am64x_evm_a53_defconfig: Switch to per-cpu timer as tick providerVignesh Raghavendra2022-04-041-3/+0
| | | | | | | | | | | | | | | | | | | | On arm64 systems, recommendation is to use per-cpu timer for time keeping. Currently AM64 ends up using DM timer as tick timer as driver is enabled in the config. Drop OMAP DM Timer related configs, this will switch to using armv8 per-cpu timer as tick timer for A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-By: Nishanth Menon <nm@ti.com>
| * configs: am64x_evm_r5_defconfig: Add support for ESMHari Nagalla2022-04-041-0/+1
| | | | | | | | | | | | | | Enable ESM driver for AM64x R5 SPL/u-boot builds. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * arch: arm: mach-k3: am642_init: Probe ESM nodesHari Nagalla2022-04-041-4/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On AM64x devices, it is possible to route Main ESM0 error events to MCU ESM. MCU ESM high error output can trigger the reset logic to reset the device. So, for these devices we expect two ESM device nodes in the device tree, one for Main ESM and the another MCU ESM in the device tree. When these ESM device nodes are properly configired it is possible to route the Main RTI0 WWDT output to the MCU ESM high output through Main ESM and trigger a device reset when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node configurations. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * arm: dts: k3-am64: Add support for ESM device nodesHari Nagalla2022-04-043-0/+39
| | | | | | | | | | | | | | | | Enable access to ESM0 configuration space and add Main ESM0 and MCU ESM nodes to the AM64 device tree. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * misc: k3_esm: Add functionality to set and route error events within K3SoCHari Nagalla2022-04-041-3/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add functionality to enable, set priority to the input events and to route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main ESM0 error events to MCU ESM. When these error events are routed to MCU ESM high output, it can trigger the reset logic to reset the device, when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'. K3 based J7 devices (ex: J721e) also have ESM modules, and the changes to the driver does not impact those devices. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * board: axy17lte: get board usable - add bootcmd and docsDzmitry Sankouski2022-04-045-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot is intended to replace linux kernel in android boot image(ABL), and it's FIT payload to replace initramfs file. The boot process is similar to boot image with linux: - android bootloader (ABL) unpacks android boot image - ABL sets `linux,initrd-start property` in chosen node in unpacked FDT - ABL sets x0 register to FDT address, and passes control to u-boot - u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable - u-boot reads `linux,initrd-start` property, and stores it in `prevbl_initrd_start_addr` In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env variable, and boils down to `bootm $prevbl_initrd_start_addr`. If more control on boot process is desired, pack a boot script in FIT image, and put it to default configuration What done: - Rearrange defconfig option order - Add CONFIG_SAVE_PREV_BL_* options - Doc updates: - remove wrong SBOOT memory corruption note, because memory is changed during u-boot bringup process, not by SBOOT - put payload on ramdisk place in abl boot image creation step Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
| * board: starqltechn: get board usable - add bootcmd and docsDzmitry Sankouski2022-04-046-14/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot is intended to replace linux kernel in android boot image(ABL), and it's FIT payload to replace initramfs file. The boot process is similar to boot image with linux: - android bootloader (ABL) unpacks android boot image - ABL sets `linux,initrd-start property` in chosen node in unpacked FDT - ABL sets x0 register to FDT address, and passes control to u-boot - u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable - u-boot reads `linux,initrd-start` property, and stores it in `prevbl_initrd_start_addr` In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env variable, and boils down to `bootm $prevbl_initrd_start_addr`. If more control on boot process is desired, pack a boot script in FIT image, and put it to default configuration What done: - strip unneeded config options - add FIT image support - add framebuffer node, u-boot logo and video console - increase LMB_MAX_REGIONS, to store all linux dtb reserved memory regions - add linux kernel image header Uart driver causes hang, when u-boot is used in android boot image instead of linux. Temporary disable console driver, until investigated and fixed. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com>
| * arm: init: save previous bootloader dataDzmitry Sankouski2022-04-045-0/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When u-boot is used as a chain-loaded bootloader (replacing OS kernel), previous bootloader leaves data in RAM, that can be reused. For example, on recent arm linux system, when chainloading u-boot, there are initramfs and fdt in RAM prepared for OS booting. Initramfs may be modified to store u-boot's payload, thus providing the ability to use chainloaded u-boot to boot OS without any storage support. Two config options added: - SAVE_PREV_BL_INITRAMFS_START_ADDR saves initramfs start address to 'prevbl_initrd_start_addr' environment variable - SAVE_PREV_BL_FDT_ADDR saves fdt address to 'prevbl_fdt_addr' environment variable Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Tom Rini <trini@konsulko.com>
| * qemu-arm: Enable NVMe for distro bootAlexander Graf2022-04-041-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | We already support the NVMe commands and PCIe backend in the QEMU target, so let's make it easy for anyone to consume them and enable NVMe distro boot along the way! With this patch, I can put an NVMe backed disk image into my QEMU VM and have it automatically load a UEFI target blob. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
* | Merge tag 'xilinx-for-v2022.07-rc1-v2' of ↵Tom Rini2022-04-0531-82/+493
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
| * | net: zynq_gem: Add SGMII dynamic config supportT Karthik Reddy2022-04-051-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for SGMII dynamic configuration which will takes care of configuring SGMII in the GEM secure (GEM_CLK_CTRL) configuration register. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a8915186e44015959978d080a31de652f544cd4a.1648631275.git.michal.simek@xilinx.com
| * | firmware: firmware-zynqmp: Add zynqmp_pm_set_gem_config apiT Karthik Reddy2022-04-052-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Add zynqmp_pm_set_gem_config() api to configure GEM secure registers. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f69e32355c6a6be7d2780663353c52757530207d.1648631275.git.michal.simek@xilinx.com
| * | gpio: slg7xl45106: Update gpio desc flags from DTT Karthik Reddy2022-04-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current slg7xl45106 gpio driver xlate() function we are not updating gpio flags from DT. Read the given flag from DT and update the gpio desc flags variable with required gpio direction state. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a8d7b4799337bd99f61ace509889f02b192a9414.1648631275.git.michal.simek@xilinx.com
| * | net: zynq_gem: Move ethernet info print statementT Karthik Reddy2022-04-051-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we are not reading the PHY address in case of CONFIG_ETH_PHY in plat function, phy address always prints as -1. So move the ethernet info print statement to probe function, to display proper phy address. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f6efc6719d767b1bebe65987c22c6d52329f4225.1648631275.git.michal.simek@xilinx.com
| * | net: phy: Avoid phy gpio reset sequence if DM_ETH_PHY is enabledT Karthik Reddy2022-04-051-19/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If DM_ETH_PHY config is enabled PHY gpio reset is taken care by the eth-phy-uclass driver, so use the PHY gpio reset functionality from ethernet_id file when this config is disabled to reset the PHY. Use debug() print instead of dev_err() to avoid warning incase if phy-id compatible string is not present. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/4d0fd3f9f886c1d943776025e5efb5438b0eb389.1648631275.git.michal.simek@xilinx.com
| * | net: zynq_gem: Use shared MDIO bus support for zynqmpMichal Simek2022-04-051-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ETH_PHY enables support to utilize generic ethernet phy framework. Though if ethernet PHY node is in other ethernet node, it will use shared MDIO to access the PHY of other ethernet. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Link: https://lore.kernel.org/r/337b1a38ba36cde1951739af62fb3d2736d97f53.1648631275.git.michal.simek@xilinx.com
| * | dt-bindings: xilinx: Add missing ids for PDMichal Simek2022-04-052-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | There are some new power domain IDs which are used in Linux kernel that's why add them here too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/e6092e1d3766c0ac11bf620820739c93ab677a85.1648626981.git.michal.simek@xilinx.com
| * | arm64: zynqmp: Record ID code for XCZU1EG deviceMichal Simek2022-04-051-0/+5
| | | | | | | | | | | | | | | | | | | | | Add ID code for 1eg device. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/5b6c9f6a25bba076f304bc4699f6f676a929a683.1648619516.git.michal.simek@xilinx.com
| * | net: phy: Fix rgmii-id phy reset timeout issueT Karthik Reddy2022-04-053-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While creating a phy device using phy_device_create(), we need to provide a valid phyaddr instead of 0 causing phy address being registered as 0 with mdio bus and shows mdio phy list as below ZynqMP> mdio list eth0: 0 - TI DP83867 <--> ethernet@ff0b0000 eth1: 0 - TI DP83867 <--> ethernet@ff0c0000 Also PHY soft reset is being requested on 0 instead of valid address causing "PHY reset timed out" error. So add phyaddr argument to phy_connect_phy_id() and to its prototype to create phy device with valid phyaddress. Fixes: a744a284e354 ("net: phy: Add support for ethernet-phy-id with gpio reset") Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Link: https://lore.kernel.org/r/fe35fddb9faa5af577ffdfabaec6879c935a30f8.1648562755.git.michal.simek@xilinx.com
| * | clk: zynqmp: Add support for for DP audio/video clocksMichal Simek2022-04-051-0/+7
| | | | | | | | | | | | | | | | | | | | | Add support for getting rate for DP audio and video clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/8792efe1fd9715f7c8a2e1e24f0454fb5b25d833.1648552434.git.michal.simek@xilinx.com
| * | xilinx: Increase max size of image from 60 to 100MBMichal Simek2022-04-052-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Recently big Linux kernels can have more then 60MB that's why increase this limit to also cover these large kernels. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f52f7c8ea419d69b248ba1460a96d1635194e128.1648551279.git.michal.simek@xilinx.com
| * | arm: zynqmp: Enable PWM command and cadence ttc pwm driverMichal Simek2022-03-301-0/+3
| | | | | | | | | | | | | | | | | | | | | Enable PWM ttc driver and command in generic image. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a660c8f2010f4f07534753e0ac44a34b8ff0d3c3.1634303847.git.michal.simek@xilinx.com
| * | pwm: Add driver for cadence TTCMichal Simek2022-03-304-0/+270
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TTC has three modes of operations. Timer, PWM and input counters. There is already driver for timer under CADENCE_TTC_TIMER which is used for ZynqMP R5 configuration. This driver is targeting PWM which is for example configuration which can be used for fan control. The driver has been tested on Xilinx Kria SOM platform where fan is connected to one PL pin. When TTC output is connected via EMIO to PL pin TTC pwm can be configured and tested for example like this: pwm config 0 0 10000 1200 pwm enable 0 0 pwm config 0 0 10000 1400 pwm config 0 0 10000 1600 Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/915a662ddb88f7a958ca1f307e8fea59af9d7feb.1634303847.git.michal.simek@xilinx.com
| * | timer: cadence: Add bind function to driverMichal Simek2022-03-301-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When DT node has pwm-cells property it shouldn't be bind as timer driver but as PWM driver. That's why make sure that this property is checked. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/434ef195fbedea9f83672a12d1ace0da16e8832e.1634303847.git.michal.simek@xilinx.com
| * | mmc: zynq_sdhci: Fix SDx_BASECLK configurationAshok Reddy Soma2022-03-291-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DLL mode supported SD reference clocks are 50 MHz, 100 MHz and 200 MHz. When user select SD frequency as 200MHz in the design, the actual frequency is going to come around ~187MHz (<= 200MHz considering the parent clock and divisor selection). We need to set SDx_BASECLK as 200 in this case, setting 187 will result in tuning failures in mmc. Set SDx_BASECLK to exact value of 200, 100 or 50 based on the frequency range. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Link: https://lore.kernel.org/r/6c1e5eeeedd2864a0c85e6b409d182031d8c6c1a.1648210268.git.michal.simek@xilinx.com
| * | serial: zynq: Change fifo behavior in debug modeMichal Simek2022-03-291-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serial IP has output buffer which status is indicated by two bits. If fifo if empty or full. Default configuration is that chars are pushed to fifo till it is full. Time to time it is visible that chars are scambled and logs are not visible. Not sure what it is exactly happening but all the time it helps to change driver behavior to write only one char at a time. That's why enable this mode when debug uart is enabled not to see scrambled chars in debug by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/332b2106d7a8190dd1001b5387f8bd1fba2e061b.1648205405.git.michal.simek@xilinx.com
| * | arm64: zynqmp: Remove low level UART setting contMichal Simek2022-03-297-40/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no reason to do serial initialization. Uart driver does it already based on DT. Good effect is that it is clear which interface is console. The same change was done in past by commit 84d2bbf082fa ("arm64: zynqmp: Remove low level UART setting"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/91a73f292bafc4b64ed09954cc23780496da4b65.1648125082.git.michal.simek@xilinx.com
| * | dt-bindings: phy: Sync phy.h with Linux kernelMichal Simek2022-03-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that both files are in sync to have the same values in DTs. The patch is fixing SPDX license as is used in the kernel and adding new values for PHY_TYPE_DPHY and PHY_TYPE_CPHY. SPDX license change was done by: Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de and new value added by: Link: https://lore.kernel.org/r/20210617144349.28448-3-jonathan@marek.ca Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/06dbc03d4c9ac5d621341d8fb8cc16f489062b39.1648113469.git.michal.simek@xilinx.com
| * | arm64: versal: Do not place u-boot to reserved memory locationMichal Simek2022-03-291-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Versal can also have reserved space in DT which u-boot has to avoid to placing self to that location. The same change was done in ZynqMP by commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location") and also for microblaze by commit d7b5cc89d329 ("microblaze: Do not place u-boot to reserved memory location"). The patch was tested by adding reserved-memory node to DT and check via bdinfo back. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/15426fa6d64835dd23c5c8c12bbfc97306fb6098.1647527129.git.michal.simek@xilinx.com
| * | firmware: zynqmp: Do not bind PD driver in SPL if disabledMichal Simek2022-03-291-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Change if condition to cover SPL flow. SPL needs to have CONFIG_SPL_POWER_DOMAIN enabled to be able to bind CONFIG_ZYNQMP_POWER_DOMAIN driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/8e1d381013a0ce39d736da166d2b401c4b12d38a.1646064792.git.michal.simek@xilinx.com
| * | arm64: zynqmp: Add resets property to sdhci nodesSai Krishna Potthuri2022-03-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "resets" property to sdhci nodes. resets property is used to reset the SD host controller when dynamic configuration support is enabled. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/f1fe39259c45a37aae56c2835ee8ba187c889d25.1646060367.git.michal.simek@xilinx.com
* | | Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2022-04-0556-563/+2325
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
| * | sunxi: defconfig: enable eMMC boot partition supportAndre Przywara2022-04-055-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the SPL can safely detect whether it was loaded from an eMMC boot partition or the normal user data partition, let's enable this feature on some boards that feature eMMC storage. That covers the boards where I could test this on, and allows the same build to be written to an SD card, eMMC user partition, eMMC boot partition, or into SPI NOR flash. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | sunxi: eMMC: Improve automatic boot source detectionAndre Przywara2022-04-051-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the Allwinner BROM loads the SPL from an eMMC boot partition, it sets the boot source byte to the same value as when booting from the user data partition. This prevents us from determining the boot source to load U-Boot proper from the proper partition for sure. The generic SPL MMC code already looks at the enabled boot partition number, to load U-Boot proper from the same partition, but this fails if there is nothing bootable in this partition, as the BROM then silently falls back to the user data partition, which the SPL misses. To learn about the actual boot source anyway, we repeat the algorithm the BROM used to select the boot partition in the first place: - Test EXT_CSD[179] to check if an eMMC boot partition is enabled. - Test EXT_CSD[177] to check for valid MMC interface settings. - Check if BOOT_ACK is enabled. - Check the beginning of the first sector for a valid eGON signature. - Load the whole SPL. - Recalculate the checksum to verify the SPL is valid. If one of those steps fails, we bail out and continue loading from the user data partition. Otherwise we load from the selected boot partition. Since the boot source is needed twice in the boot process, we cache the result of this test to avoid doing this costly test multiple times. This allows the very same image file to be put onto an SD card, into the eMMC user data partition or into the eMMC boot partition, and safely loads the whole of U-Boot from there. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | spl: mmc: extend spl_mmc_boot_mode() to take mmc argumentAndre Przywara2022-04-0414-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Platforms can overwrite the weak definition of spl_mmc_boot_mode() to determine where to load U-Boot proper from. For most of them this is a trivial decision based on Kconfig variables, but it might be desirable the probe the actual device to answer this question. Pass the pointer to the mmc struct to that function, so implementations can make use of that. Compile-tested for all users changed. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA) Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3) Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sunxi: clock: H6: Adjust PLL LDO before clock setupJernej Skrabec2022-04-041-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | BSP boot0 adjust PLL LDO regulator before clocks are initialized. Let's do that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | sunxi: clock: H6/H616: Add resistor calibrationJernej Skrabec2022-04-041-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | BSP boot0 executes resistor calibration before clocks are initialized. Let's do that. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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