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* Add morphbaserock/james/tegra-uboot-btrfsbaserock/arm/tegra-uboot-btrfsJames Thomas2014-08-031-0/+23
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* Add btrfs boot to tegra configJames Thomas2014-07-221-0/+5
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* HACK! Don't mangle, just strip!James Thomas2014-07-221-3/+5
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* Add btrfs support to cmd_pxeJames Thomas2014-07-222-0/+18
| | | | Build btrfs support for tegra boards
* Introduces btrfs file-system to read file fromAdnan Ali2014-07-2212-0/+1964
| | | | | | | volume/sub-volumes with btrload command. This implementation has read-only support. This btrfs implementation is based on syslinux btrfs code
* cmd_mmc.c: fix typo when checking mmc_init()Bryan Wu2014-05-221-1/+1
| | | | | | | | | | | | | | Typo makes mmc dev command always return 1 as false. This patch fix this. Bug 200006872 Change-Id: I4730d764363dc3f851aa7bfc53417e65e1824c38 Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/412966 GVS: Gerrit_Virtual_Submit Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
* cmd_mmc.c: check mmc_init() during mmc devBryan Wu2014-05-211-1/+3
| | | | | | | | | | | | | | | | | | | | | mmc dev ${devnum} will return 0 as success even if there is no card inserted. Booting script like tegra-common-post.h will call mmc dev ${devnum} to check the mmc device status, it always return 0 even if mmc_init() fails. Check mmc_init() return value let mmc dev command return failure when mmc_init() fails. Bug 200004721 Bug 1482099 Change-Id: Ida166777b62c0906912394bb06bbc083251c458d Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/410665 Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Jong Kim <jongk@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
* Tegra: common: add ft_board_setup supportBryan Wu2014-05-202-0/+138
| | | | | | | | | | | | | | | | | | ft_board_setup() provides a hook for U-Boot to overwrite some properties in DT file which will be passed to kernel. Tegra version of ft_board_setup() will firstly overwirte board info related serial numbers in DT file. Also update config files for Tegra as well. Bug 200005196 Bug 1482099 Change-Id: Ide208139618cab12d355dcc48a407e5ea62a31ee Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: http://git-master/r/411664 Reviewed-by: Winnie Hsu <whsu@nvidia.com>
* ARM: tegra: add warmboot support for Tegra124Bryan Wu2014-04-2416-3/+2251
| | | | Signed-off-by: Bryan Wu <pengw@nvidia.com>
* Tegra: Use mem size in memory controller instead of ODMDataBryan Wu2014-04-222-1/+14
| | | | | | | | | | | | | | | | | Read MC_EMEM_CFG (offset 50h) to get EMEM_SIZE_MB, shift it left to be ODMDATA compatible (bits 31:28), and use it instead of ODMDATA on Venice. ODMDATA isn't available currently because NVFlash/bootloader.bin don't work on Venice (yet). Another option would be to modify the CrOS script that creates the BCT and embed an ODMDATA at that time, but this change is more forward-looking, since we don't really use ODMDATA for anything but the RAM size bits. Change-Id: I105f7a7d476f343b6e0a93246fb97699106a8d53 Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61511 Signed-off-by: Bryan Wu <pengw@nvidia.com>
* ARM: tegra: increase buffer size and sys args numBryan Wu2014-04-181-2/+2
| | | | | | | | | | | | | | | Tegra kernel booting needs a long bootargs command line. Default value of CONFIG_SYS_CBSIZE is too small to printf out the long command line and will cause system panic. Default value of CONFIG_SYS_MAXARGS is too small to setenv bootargs as the long command line, then kernel won't boot without the complete bootargs. Increase this 2 config options solve this problem. Signed-off-by: Bryan Wu <pengw@nvidia.com>
* ARM: tegra: Disable VPRBryan Wu2014-04-175-0/+93
| | | | | | | | | | | | | | | On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed. This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Bryan Wu <pengw@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/180322
* ARM: tegra: add Jetson TK1 boardStephen Warren2014-03-148-0/+428
| | | | | | | | | Jetson TK1 and Venice2 are very similar boards, at least as far as theHW components that U-Boot supports so far. Hence, add the Jetson TK1 board as a variant of the Venice2 board, so we don't have to duplicate any code or pinmux tables. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Tegra124 pinmux cleanupStephen Warren2014-03-145-744/+706
| | | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra124_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. There are differences in the set of drive groups. I have validated this against the TRM. There are differences order of pin definitions in pinmux.c; these previously had significant mismatches with the correct order:-( I adjusted a few entries in pinmux-config-venice2.h since the set of legal functions for some pins was updated to match the TRM. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: Tegra114 pinmux cleanupStephen Warren2014-03-145-753/+680
| | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra114_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted a few entries in pinmux-config-dalmore.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: Tegra30 pinmux cleanupStephen Warren2014-03-145-1151/+1082
| | | | | | | | | | | | | | | | | | | | | | This renames all the pinmux pins, drive groups, and functions so they have a prefix which matches the type name. These lists are also auto- generated using scripts that were also used to generate the kernel pinctrl drivers. This ensures that the lists are consistent between the two. The entries in tegra30_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. This introduces a few changes to pin/group/function naming and the set of available functions for each pin. The new values now exactly match the TRM; the chip documentation. I adjusted one entry in pinmux-config-cardhu.h due to this. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: Tegra20 pinmux cleanupStephen Warren2014-03-1412-412/+397
| | | | | | | | | | | | | | This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: pinmux naming consistency fixesStephen Warren2014-03-1419-217/+223
| | | | | | | | | | | | | | | Clean up the naming of pinmux-related objects: * Refer to drive groups rather than pad groups to match the Linux kernel. * Ensure all pinmux API types are prefixed with pmux_, values (defines) are prefixed with PMUX_, and functions prefixed with pinmux_. * Modify a few type names to make their content clearer. * Minimal changes to SoC-specific .h/.c files are made so the code still compiles. A separate per-SoC change will be made immediately following, in order to keep individual patch size down. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: reduce public pinmux APIStephen Warren2014-03-142-8/+2
| | | | | | | | | | | Remove a few unused functions from the pinmux header. They aren't currently used, and removing them prevents any new usage from appearing. This will ease moving to just pinmux_config_table() and padgrp_config_table() in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: pinctrl: remove duplicationStephen Warren2014-03-1414-2079/+738
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the duplication by creating pinmux-common.c for all the identical code. This leaves: * arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of the various pins/pin groups, drive groups, and mux functions. * arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table stating which pin groups support which mux functions. The code in pinmux-common.c is semantically identical to that in the various original pinmux.c, but had some consistency and cleanup fixes applied during migration. I removed the definition of struct pmux_tri_ctlr, since this is different between SoCs (especially Tegra20 vs all others), and it's much simpler to deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c, and warmboot_avp.c needed updates due to this, since they previously hijacked this struct to encode the location of some non-pinmux registers. Now, that code simply calculates these register addresses directly using simple and obvious math. I like this method better irrespective of the pinmux code cleanup anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* ARM: tegra: prototype pinmux_init() in board.hStephen Warren2014-03-145-11/+7
| | | | | | | | | | pinmux_init() is a board-level function, not a pinmux driver function. Move the prototype to a board header rather than the driver header. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> --- Sent V1
* ARM: tegra: pinctrl: make pmux_func values consistent on Tegra20Stephen Warren2014-03-142-11/+10
| | | | | | | | | | | | | | | | | | For consistency with other SoCs, modify Tegra20's enum pmux_func to: * Remove PMUX_FUNC values that aren't real * Use the same PMUX_FUNC_RSVD[1-4] values, and ensure (RSVD1 & 3)==0; this will be assumed by pinmux_set_func() in a future patch. Unfortunately, PMUX_FUNC_RSVD is still used in the pin macros. Use a private define inside the driver to prevent this from causing compilaton errors. This will be cleaned up when the pin tables are re-written in a later patch in this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> --- Sent V1
* ARM: tegra: pinctrl: remove vddioStephen Warren2014-03-148-86/+0
| | | | | | | | | | | This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> --- Sent V1
* ARM: tegra: pinctrl: remove func_safeStephen Warren2014-03-148-24/+0
| | | | | | | | | | | This field isn't used anywhere, so remove it. Note that PIN() macros are left unchanged for now, to avoid many diffs to them; later commits will completely rewrite them just one time. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> --- Sent V1
* ARM: tegra: make all I2C ports open-drainStephen Warren2014-03-132-16/+16
| | | | | | | | | | | I2C protocol requires open-drain IOs. Fix the Dalmore and Venice2 pinmux tables to configure the IOs correctly. Without this, Tegra may actively drive the lines high while an external device is actively driving the lines low, which can only lead to bad things. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- Sent V1
* boards.cfg: Run the reformatter scriptTom Rini2014-03-111-20/+20
| | | | | | Some recent changes got parts of the file out of order again, correct. Signed-off-by: Tom Rini <trini@ti.com>
* boards.cfg: move boards with invalid emails to OrphanMasahiro Yamada2014-03-111-60/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When I cc board maintainers, some of them result in bounce mails. It turned out the following do not work any more: Yuli Barcohen <yuli@arabellasw.com> Travis Sawyer <travis.sawyer@sandburst.com> Yusdi Santoso <yusdi_santoso@adaptec.com> David Updegraff <dave@cray.com> Sangmoon Kim <dogoil@etinsys.com> Anton Vorontsov <avorontsov@ru.mvista.com> Blackfin Team <u-boot-devel@blackfin.uclinux.org> Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> Andre Schwarz <andre.schwarz@matrix-vision.de> For the blackfin boards where Sonic Zhang is also listed as a maintainer, dead addresses should be simply dropped. For all of the others, the status should be changed to "Orphan". We have adopted the definition of "Orphan" as: board is not actively maintained any more but still builds, and any address associated with it is that of the last known maintainer(s) Even though the emails do not work any more, they carry information. We want to keep them. Besides, Orphan boards have been collected at the bottom of boards.cfg. (This is done when we run "tools/reformat.py") Add separators to distinguish them from those which were moved to Orphan 6 months ago. I believe it will be helpful in future to find which boards are old enough to be removed from the code base. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Detlev Zundel <dzu@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Prepare v2014.04-rc2v2014.04-rc2Tom Rini2014-03-101-1/+1
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-03-1061-91/+983
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| * arm: atmel: sama5d3: add nand spl boot supportBo Shen2014-03-094-0/+18
| | | | | | | | | | | | | | Add NAND SPL boot support with hardware PMECC. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * mtd: nand: atmel: prepare for nand spl boot supportBo Shen2014-03-092-0/+214
| | | | | | | | | | | | | | | | | | Prepare for nand spl boot support. It supports nand software ECC and hardware PMECC. This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: atmel: sama5d3: add spi spl boot supportBo Shen2014-03-094-0/+17
| | | | | | | | | | | | | | Add SPI SPL boot support for sama5d3xek board. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: atmel: add sama5d3 Xplained board supportBo Shen2014-03-094-0/+350
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sama5d3 Xplained board support which use Atmel SAMA5D36 SoC. Now it supports boot from NAND flash and SD/MMC card. Features support: - NAND flash - SD/MMC card - Two USB hosts - Ethernet (one GMAC, one EMAC) Signed-off-by: Bo Shen <voice.shen@atmel.com> [reorder boards.cfg] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * at91 gpio: fix typo in compatibility macroAndreas Henriksson2014-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | It's called _pio_ in the version that was added to git. Apparently it got renamed without updating the macros before it was applied, c.f. http://u-boot.10912.n7.nabble.com/U-Boot-PATCH-3-9-V3-add-a-new-AT91-GPIO-driver-td75922.html Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * at91sam9263ek: add mmc supportAndreas Henriksson2014-03-093-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for using the Atmel MCI driver on at91sam9263ek. This change is modeled after the existing at91sam9260ek support. Please note that this hooks up slot1 (MCI1) for SD. Not both. Tested with at91bootstrap and u-boot on dataflash in slot 0 and fat-formatted 8GB SDHC in slot 1 on first revision at91sam9263ek (which must use dataflash in slot0 to boot). CONFIG_ATMEL_MCI_PORTB not tested. Signed-off-by: Andreas Henriksson <andreas.henriksson@endian.se> [remove empty line] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2014-03-0714-51/+95
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| | * ARM: tegra: implement bootcmd_pxeStephen Warren2014-03-054-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | This retrieves a PXE config file over the network, and executes it. This allows an extlinux config file to be retrieved over the network and executed, whereas the existing bootcmd_dhcp retrieves a U-Boot script. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: rework boot scriptsStephen Warren2014-03-051-9/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the common Tegra boot scripts in the default environment to a) Make use of the new "test -e" shell command to avoid some error messages. b) Allow booting using the sysboot command and extlinux.conf. This allows easy creation of boot menus, and provides a simple interface for distros to parameterize/configure the boot process. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: convert tegra to use distro defaultsStephen Warren2014-03-051-16/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Modify all Tegra boards to include the "distro defaults" header, so that all the config options distros expect are enabled. Remove any #defines that enable the same options from the Tegra files. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: set CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTSStephen Warren2014-03-054-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's EHCI controllers only have a single PORTSC register. Configure U-Boot to know this. This prevents e.g. ehci_shutdown() from touching non-existent registers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: simplify halt_avp()Stephen Warren2014-03-051-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to completely halt the AVP processor, we should simply write FLOW_MODE_STOP without any extra options that allow wakeup. Amend the code to do this. I believe that enabling FIQ_1 and IRQ_1 allow the CPU to be awoken by interrupts. We don't want this; if later SW wishes to use the AVP, it should be reset and booted from scratch. Related, the bits that were previously IRQ_1 and FIQ_1 have a slightly different definition starting with Tegra114, so the values we're writing don't entirely make sense there anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: fix NV_PA_CSITE_BASE for Tegra124Stephen Warren2014-03-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Tegra124 moved the CSITE block's base address. Fix U-Boot to use the correct address. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: fix pmc_pwrgate_timer_mult register definitionStephen Warren2014-03-052-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register pmc_pwrgate_timer_mult has a different layout on Tegra114 and Tegra124. Reflect this in pmc.h. Also, simply write the whole of the register in start_cpu() rather than doing a read-modify-write; the register is simple enough that the code can easily construct the entire desired value. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * ARM: tegra: move CONFIG_TEGRAnnStephen Warren2014-03-058-20/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | <asm/arch-tegra/tegra.h> needs to use CONFIG_TEGRA* to conditionalize some definitions, since some modules moved between generations. Move the definition of CONFIG_TEGRAnn to a header that's included earlier, so that it's set by the time tegra.h needs to use it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | OMAP3: igep00x0: Enable required clocks for GPIO that are used.Enric Balletbo i Serra2014-03-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable required clocks for GPIO to fix a boot issue introduced by commit f33b9bd3984fb11e1d8566a866adc5957b1e1c9d (arm: omap3: Enable clocks for peripherals only if they are used). Without this patch the u-boot freezes after the following messages OMAP36XX/37XX-GP ES1.2, CPU-OPP2, L3-200MHz, Max CPU Clock 1 Ghz IGEPv2 + LPDDR/NAND I2C: ready DRAM: 512 MiB NAND: 512 MiB MMC: OMAP SD/MMC: 0 Diving into the issue, the sequence that produces the u-boot freezes is setup_net_chip |--> gpio_direction_out |--> _set_gpio_dataout |--> __raw_writel To avoid this we just need enable the clocks for GPIOs that are used, but it would be interesting implement a mechanism to protect these situations and make sure that the clock is enabled when we request a GPIO. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
| * | board/BuR/common: fix phy addressesHannes Petermaier2014-03-061-2/+2
| |/ | | | | | | | | | | | | | | B&R boards are using Phy Addresses 'one' and 'two', prior this was defined through #define PHYADDR 1 within a header file. Now this is addresses are given with device-driver structure. Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
| * arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootupStefan Roese2014-03-043-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Since the switch may be re-configured for VLAN usage in Linux (or any other OS), lets reset the switch to its default register values upon power-up. Otherwise network might not be available in U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Roger Meier <r.meier@siemens.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com> Cc: Tom Rini <trini@ti.com>
| * ARM: AM43xx: Change DDR3 Reset ValueDave Gerlach2014-03-041-1/+1
| | | | | | | | | | | | | | | | | | The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value of the ddr reset value for DDR3 before the EMIF takes over. We must have this bit set high so that on exit from DeepSleep0 within the kernel the reset line has the proper value. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ARM: AM43xx: Write sdram_config to secure_emif_sdram_configDave Gerlach2014-03-041-0/+1
| | | | | | | | | | | | | | | | | | The register secure_emif_sdram_config in control module is copied to the EMIF sdram_config register when it is coming out of DeepSleep0 in order to ensure that the EMIF comes up for the correct type of DDR. Without this, resume can hang from within the kernel. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ARM: AM43xx: EMIF: configure self-refresh entry delayDave Gerlach2014-03-041-2/+2
| | | | | | | | | | | | | | | | | | | | Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the desired delay in cycles that the EMIF waits without an access to enter self-refresh, in this case 8192 cycles. With this, code desiring to enter self refresh only has to toggle one bit to enable it. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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