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* Merge tag 'efi-2021-10-rc5' of ↵WIP/26Sep2021Tom Rini2021-09-264-23/+35
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc5 Documentation: * add /config bindings to HTML documentation UEFI * Fix number_of_algorithms field in TCG EFI Protocol
| * efi_loader: Fix spec ID event creationRuchika Gupta2021-09-252-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TCG EFI Protocol Specification defines the number_of_algorithms field in spec ID event to be equal to the number of active algorithms supported by the TPM device. In current implementation, this field is populated with the count of all algorithms supported by the TPM which leads to incorrect spec ID event creation. Similarly, the algorithm array in spec ID event should be a variable length array with length being equal to the number_of_algorithms field. In current implementation this is defined as a fixed length array which has been fixed. Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org> CC: Masahisa Kojima <masahisa.kojima@linaro.org> CC: Ilias Apalodimas <ilias.apalodimas@linaro.org> CC: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
| * doc: Add mention of the /config bindingSimon Glass2021-09-252-0/+11
|/ | | | | | | | | | The devicetree binding files are in their own directory and use a simple text format. Add a link for the binding for the /config node, since it is otherwise hard to find. Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* Merge branch '2021-09-24-assorted-minor-updates'Tom Rini2021-09-2413-685/+42
|\ | | | | | | - Assorted bugfixes, MAINTAINER updates and dead code removal
| * arm: orion5x: edminiv2: change maintainerWIP/2021-09-24-assorted-minor-updatesSimon Guinot2021-09-241-1/+1
| | | | | | | | | | | | | | | | | | Since Albert Aribaud is not maintaining anymore the LaCie Ethernet Disk mini V2 board, then I am taking over. Signed-off-by: Simon Guinot <simon.guinot@sequanux.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * mtd: remove SPEAr flash driver st_smiPatrick Delaunay2021-09-245-668/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove the driver st_smic.c used in SPEAr products and the associated config CONFIG_ST_SMI; this driver is no more used in U-Boot after the commit 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support"). Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Taking over responsibility for GE boards from SebastianMartyn Welch2021-09-243-3/+3
| | | | | | | | | | | | | | | | I am taking over responsibility for the GE board from Sebastian Reichel. Updating the MAINTAINERS files to reflect this. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| * MAINTAINERS: remove SPEAR entryPatrick Delaunay2021-09-241-7/+0
| | | | | | | | | | | | | | | | | | | | | | As the lastest spear directories are removed, delete the associated entry in the MAINTAINERS file: - arch/arm/cpu/arm926ejs/spear/ - arch/arm/include/asm/arch-spear/ Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * fs: avoid superfluous messagesHeinrich Schuchardt2021-09-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Output like the following is quite irritating: => bootefi hello Scanning disk mmc2.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Scanning disk mmc1.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Scanning disk mmc0.blk... No valid Btrfs found Bad magic number for SquashFS image. ** Unrecognized filesystem type ** Albeit a whole disk may be formatted with a filesystem in most cases a partition table is used and the whole disk (partition number 0) doesn't contain a filesytem. Some partitions may only contain a blob. Not seeing a filesytem on the whole disk or on any partition is only worth a debug message. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * scripts/mailmapper: enable running with Python 3Heinrich Schuchardt2021-09-241-5/+9
| | | | | | | | | | | | | | | | Our mailmapper script required Python 2 which is no longer maintained. A main difference when converting to Python 3 is that byte strings are not character strings. So add conversion and skip over conversion errors. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
| * test/py: tpm2: Skip tpm pytest based on env variableT Karthik Reddy2021-09-241-0/+28
|/ | | | | | | | | | | | Tpm test cases relies on tpm device setup. Provide an environment variable "env__tpm_device_test_skip = True" to skip the test case if tpm device is not present. Only needed will have to add variable to the py-test framework. Test runs successfully even this variable is absent. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* Merge git://source.denx.de/u-boot-socfpgaWIP/23Sep2021Tom Rini2021-09-235-20/+11
|\ | | | | | | Bugfixes for this one socfpga platform
| * ddr: altera: use KBUILD_BASENAME instead of __FILE__Marek Vasut2021-09-221-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The KBUILD_BASENAME contains just the name of the compiled module, in this case 'sequencer', rather than a full path to the compiled file. Use it to prevent pulling the full path into the U-Boot binary, which is useless and annoying. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Let DWMAC configure PHY reset GPIOMarek Vasut2021-09-221-7/+0
| | | | | | | | | | | | | | | | | | | | | | The DM DWMAC driver is perfectly capable of configuring the ethernet PHY reset GPIO, let the driver do it instead of doing it in the board file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Enable DW I2C driverMarek Vasut2021-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | The Designware I2C IP is used to communicate with I2C peripherals on SoCFPGA, and required to access I2C EEPROM on this board. Enable it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Fix UDC controller phandle in DTMarek Vasut2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | The USB peripheral controller is the DWC2 controller 1, not 0. Update the phandle to fix UDC support on this board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Un-disable WDT in DTMarek Vasut2021-09-221-4/+0
| | | | | | | | | | | | | | | | | | The WDT on this system should be enabled, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Set default SPI NOR mode and frequencyMarek Vasut2021-09-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The SPI NOR bus mode is 0 on this system, update it accordingly. Increase frequency to 40 MHz and enable SFDP parsing, since the flashes on this system support that and it is a huge performance improvement. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital SMarek Vasut2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | This was configured in downstream, so it is likely that most of the custom software used around the device depends on it. Make upstream compatible. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Increase environment sizeMarek Vasut2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | Increase the environment size from 4k to 16k to prevent environment from becoming full. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| * arm: socfpga: vining: Drop meaningless commentMarek Vasut2021-09-221-2/+0
| | | | | | | | | | | | | | | | | | The comment is no longer meaningful due to DT conversion, drop it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* | Merge branch 'master' of git://source.denx.de/u-boot-usbTom Rini2021-09-2315-58/+327
|\ \ | |/ |/| | | Late bunch of USB fixes (incl. the xhci usb 3.1 support)
| * usb: xhci-dwc3: Add support for USB 3.1 controllersMark Kettenis2021-09-221-1/+2
| | | | | | | | | | | | | | | | This adds support for the DWC_sub31 controllers such as those found on Apple's M1 SoC. This version of the controller seems to work fine with the existing driver. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
| * usb: ehci-mx6: use phy_type from device treeMatthias Schiffer2021-09-222-2/+24
| | | | | | | | | | | | | | | | | | | | | | Allow using different PHY interfaces for multiple USB controllers. When no value is set in DT, we fall back to CONFIG_MXC_USB_PORTSC for now to stay compatible with current board configurations. This also adds support for the HSIC mode of the i.MX7. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| * usb: ehci-ci: remove redundant PORTSC flag definitionsMatthias Schiffer2021-09-221-11/+0
| | | | | | | | | | | | | | | | These definitions are unused, all boards that define portsc flags use the equivalent PORT_* definitions instead. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| * include/configs: replace MXC_EHCI_MODE_SERIAL with PORT_PTS_SERIALMatthias Schiffer2021-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | The MXC_EHCI_MODE_ definitions are redundant. Replace MXC_EHCI_MODE_SERIAL with the equivalent PORT_PTS_SERIAL. Only the zmx25 platform is affected. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| * usb: add support for ULPI/SERIAL/HSIC PHY modesMatthias Schiffer2021-09-222-0/+6
| | | | | | | | | | | | | | | | Import usb_phy_interface enum values and DT match strings from the Linux kernel. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
| * configs: Enable USB3 on Allwinner H6 boardsSamuel Holland2021-09-222-0/+10
| | | | | | | | | | | | | | | | Pine H64 and Orange Pi 3 both provide a USB3 type A port. Enable it in U-Boot. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * usb: xhci-dwc3: Add support for clocks/resetsSamuel Holland2021-09-221-0/+56
| | | | | | | | | | | | | | | | | | | | Some platforms, like the Allwinner H6, do not have a separate glue layer around the dwc3. Instead, they rely on the clocks/resets/phys referenced from the dwc3 DT node itself. Add support for enabling the clocks/resets referenced from the dwc3 DT node. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * usb: xhci-pci: Move reset logic out of XHCI coreSamuel Holland2021-09-224-43/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resetting an XHCI controller inside xhci_register undoes any register setup performed by the platform driver. And at least on the Allwinner H6, resetting the XHCI controller also resets the PHY, which prevents the controller from working. That means the controller must be taken out of reset before initializing the PHY, which must be done before calling xhci_register. The logic in the XHCI core was added to support the Raspberry Pi 4 (although this was not mentioned in the commit log!), which uses the xhci-pci platform driver. Move the reset logic to the platform driver, where it belongs, and where it cannot interfere with other platform drivers. This also fixes a failure to call reset_free if xhci_register failed. Fixes: 0b80371b350e ("usb: xhci: Add reset controller support") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * phy: sun50i-usb3: Add a driver for the H6 USB3 PHYSamuel Holland2021-09-223-0/+180
|/ | | | | | | | | This driver is needed for XHCI to work on the Allwinner H6 SoC. The driver is copied from Linux v5.10. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-x86Tom Rini2021-09-222-0/+33
|\ | | | | | | - Small fixes to eMMC and SDHCI for Intel Edison
| * x86: tangier: acpi: Add GPIO card detection to SDHCI #2Andy Shevchenko2021-09-221-0/+32
| | | | | | | | | | | | | | | | | | | | On Intel Tangier the SDHCI #2 provides SD card connection. Add GPIO card detection for it. Fixes: 39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier") BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: edison: Mark eMMC non-removableAndy Shevchenko2021-09-221-0/+1
|/ | | | | | | eMMC is non-removable on Intel Edison board. Fix the DTS accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'u-boot-stm32-20210921' of ↵Tom Rini2021-09-222-2/+6
|\ | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-stm - stm32mp15: fix the used partition name for U-Boot environement with SPL
| * arm: dts: stm32mp1: use ssbl partition name for U-BootPatrick Delaunay2021-09-212-2/+6
|/ | | | | | | | | | | | | Continue to use the "ssbl" name for GPT partition of secondary boot stage = U-Boot for basic boot with SPL to avoid to disturb existing user. The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A BL2 requirement; it the default configuration for STMicroelectronics boards. Fixes: b73e8bf453f8 ("arm: stm32mp: add defconfig for trusted boot with FIP") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2021-09-201-5/+5
|\ | | | | | | - wdt: dw: Fix passing NULL pointer to reset functions (Sean)
| * wdt: dw: Fix passing NULL pointer to reset functionsSean Anderson2021-09-201-5/+5
|/ | | | | | | | reset_*_bulk expects a real pointer. Fixes: 4f7abafe1c ("driver: watchdog: reset watchdog in designware_wdt_stop() function") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge tag 'dm-pull-18sep21' of ↵WIP/19Sep2021Tom Rini2021-09-198-180/+226
|\ | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-dm Revert the public-key-embedded-in-executable patches so this does not form part of an official release before it is agreed.
| * Revert "efi_capsule: Move signature from DTB to .rodata"Simon Glass2021-09-186-49/+4
| | | | | | | | | | | | | | | | | | | | This was unfortunately applied despite much discussion about it beiong the wrong way to implement this feature. Revert it before too many other things are built on top of it. This reverts commit ddf67daac39de76d2697d587148f4c2cb768f492. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Revert "mkeficapsule: Remove dtb related options"Simon Glass2021-09-181-7/+222
| | | | | | | | | | | | This reverts commit f86caab058ff062ce72b24cd1ab9ec1253cc1352. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Revert "doc: Update CapsuleUpdate READMEs"Simon Glass2021-09-181-124/+0
|/ | | | | | This reverts commit 316ab801c0d91c02b21b8be1e3db7e69555364e9. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch '2021-09-17-TI-platform-updates'Tom Rini2021-09-1711-131/+196
|\ | | | | | | - Assorted bugfixes for TI platforms
| * arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 ↵WIP/2021-09-17-TI-platform-updatesNishanth Menon2021-09-171-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | startup With Device Manager firmware in an elf file form, we cannot load the FIT image to the exact same address as any of the executable sections of the elf file itself is located. However, the device tree descriptions for the ARMV8 bootloader/OS includes DDR regions only the final sections in DDR where the Device Manager firmware is actually executing out of. As the R5 uC is usually operating at a slower rate than an ARMv8 MPU, by starting the Armv8 ahead of parsing the elf and copying the correct sections to the required memories creates a race condition where the ARMv8 could overwrite the elf image loaded from the FIT image prior to the R5 completing parsing and putting the correct sections of elf in the required memory locations. OR create rather obscure debug conditions where data in the section is being modified by ARMV8 OS while the elf copy is in progress. To prevent all these conditions, lets make sure that the elf parse and copy operations are completed ahead of ARMv8 being released to execute. We will pay a penalty of elf copy time, but that is a valid tradeoff in comparison to debug of alternate scenarios. Signed-off-by: Nishanth Menon <nm@ti.com>
| * arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS NorthbridgeRoger Quadros2021-09-172-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This fixup is critical to provide deterministic access latency to MSMC from ICSSG, it applies to all AM65 silicon revisions and is due to incorrect reset values (has no erratum id) and statically setting things up should be done independent of usecases and board. This specific style of Northbridge configuration is specific only to AM65x devices, follow-on K3 devices have different data prioritization schemes (ASEL and the like) and hence the fixup applies purely to AM65x. Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in case of SR1 devices, on SR2 devices, lockups were not observed so far but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower throughput. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Andrew F. Davis <afd@ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Benoit Parrot <bparrot@ti.com> [Jan: rebased, dropped used define, extended commit log] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> [Nishanth: Provide relevant context in the commit message] Signed-off-by: Nishanth Menon<nm@ti.com>
| * clk: ti: k3: Update driver to account for divider flagsSuman Anna2021-09-174-112/+118
| | | | | | | | | | | | | | | | | | | | | | | | The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-writeDave Gerlach2021-09-171-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: Add note to auto-generated filesDave Gerlach2021-09-174-4/+20
| | | | | | | | | | | | | | | | | | | | | | Add a note to the automatically generated clk-data and dev-data files for j721e and j7200 to indicate that they are in fact auto-generated and should not be hand edited. Also adjust TI URL to use https instead of http and also add an empty line before first header inclusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocksSuman Anna2021-09-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocksSuman Anna2021-09-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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