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* crc: Fix code style with crc functionsSimon Glass2019-12-024-12/+73
| | | | | | | | | | | Some of these have a space before the bracket. Drop it to fix the style. Add some missing function comments while here. Note that u32 and u8 cannot be used here since crc.h is included on the host side. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Drop linux/crc8.hSimon Glass2019-12-026-28/+22
| | | | | | | | We have an existing U-Boot header for the one function that this defines. Use that instead of the linux/ one. Move over the nice comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move random-number functions into their own headerSimon Glass2019-12-025-6/+43
| | | | | | | | Create a new rand.h header file and move functions into it, to reduce the size of common.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* status_led: Tidy up the code styleSimon Glass2019-12-023-7/+7
| | | | | | | There are a few whitespace problems with this code. Tidy them up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Drop global inclusion of status_led.hSimon Glass2019-12-0217-4/+16
| | | | | | | | This is only used by a few files so it should not be in the common header. Move it out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Drop CONFIG_SHOW_ACTIVITYSimon Glass2019-12-026-31/+0
| | | | | | This feature is not enabled by any board. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move older CPU functions to their own headerSimon Glass2019-12-0210-9/+31
| | | | | | | | These should be moved to driver model, but in the meantime, move them out of the common header to help reduce its size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-socfpgaWIP/28Nov2019Tom Rini2019-11-283-1/+24
|\ | | | | | | - Assorted Gen5 fixes
| * ARM: socfpga: Unreset NAND in SPL on Gen5Marek Vasut2019-11-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP explicitly in the platform code as the denali-spl driver is not aware of DM at all. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: socfpga: Introduce u-boot-with-nand-spl.sfp targetMarek Vasut2019-11-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND devices with 128 kiB erase blocks require extra 64 kiB padding between each SPL image. Generate U-Boot image with such a padding using this new target. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: socfpga: Add ArriaV ST/SX IDMarek Vasut2019-11-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Add new FPGA ID for ArriaV ST/D3 or SX/B3 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: socfpga: Purge pending transactions upon enabling bridges on Gen5Marek Vasut2019-11-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Gen5, when the FPGA is loaded and there was some prior interaction between the HPS and the FPGA via bridges (e.g. Linux was running and using some of the IPs in the FPGA) followed by warm reset, it has been observed that there might be outstanding unfinished transactions. This leads to an obscure misbehavior of the bridge. When the bridge is enabled again in U-Boot and there are outstanding transactions, a read from within the bridge address range would return a result of the previous read instead. Example: => bridge enable ; md 0xff200000 1 ff200000: 1234abcd => bridge enable ; md 0xff200010 1 ff200010: 5678dcba <------- this is in fact a value which is stored in a memory at 0xff200000 => bridge enable ; md 0xff200000 1 ff200000: 90effe09 <------- this is in fact a value which is stored in a memory at 0xff200010 and so it continues. Issuing a write does lock the system up completely. This patch opens the FPGA bridges in 'bridge enable' command, the tears them down again, and then opens them again. This allows these outstanding transactions to complete and makes this misbehavior go away. However, it is not entirely clear whether this is the correct solution. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
| * ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disableMarek Vasut2019-11-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register, which releases all bridges from reset, instead of putting all bridges into reset. Fix this by inverting the mask and actually putting the bridges into reset. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | Merge git://git.denx.de/u-boot-usbTom Rini2019-11-289-60/+364
|\ \ | | | | | | | | | - USB keyboard improvements
| * | sandbox: enable USB_KEYBOARD_FN_KEYSHeinrich Schuchardt2019-11-254-0/+4
| | | | | | | | | | | | | | | | | | | | | Enable the support of function keys on the USB keyboard. This is necessary to test the USB keyboard driver. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | dm: test: usb: rework keyboard testHeinrich Schuchardt2019-11-252-18/+293
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the unit test to pass full 8 byte scan code sequences to the USB keyboard emulation driver and to parse multi-byte escape sequences. The following features are not yet tested: * LED status * caps-lock * num-lock * numerical pad keys The following features are not yet implemented by the USB keyboard driver and therefore not tested: * modifiers for non-alpha-numeric keys, e.g. <SHIFT><TAB> and <ALT><F4> * some special keys, e.g. <PRINT> * some modifiers, e.g. <ALT> and <META> * alternative keyboard layouts Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | usb: kbd: move USB_KBD_BOOT_REPORT_SIZE to usb.hHeinrich Schuchardt2019-11-252-6/+6
| | | | | | | | | | | | | | | | | | | | | Move constant USB_KBD_BOOT_REPORT_SIZE. This allows us to reuse it. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | usb: kbd: implement special keysHeinrich Schuchardt2019-11-252-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | Provide support for F1-F12, Insert, Delete, Home, End, Page Up, Page Down. As this leads to a size increase provide a customizing setting CONFIG_USB_KEYBOARD_FN_KEYS. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | usb: kbd: simplify coding for arrow keysHeinrich Schuchardt2019-11-251-35/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid duplicate translation of arrow key codes. Reduce code size by avoiding strings and eliminating usb_kbd_put_sequence(). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | usb: kbd: signature of usb_kbd_put_queue()Heinrich Schuchardt2019-11-251-1/+1
| | | | | | | | | | | | | | | | | | | | | usb_kbd_buffer is defined as u8[]. So let usb_kbd_put_queue() use u8 as type of the parameter for the new byte. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | usb: kbd: fix typoHeinrich Schuchardt2019-11-251-1/+1
| |/ | | | | | | | | | | | | %s/a interrupt/an interrupt/ Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'mmc-11-27-2019' of ↵Tom Rini2019-11-2813-180/+265
|\ \ | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc update and some cleanup in ls1021a/mpc83xx code - mmc tmio sdhi update for hs400
| * | mmc: tmio: sdhi: Add calibration tablesMarek Vasut2019-11-272-17/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using single fixed value for the calibration offset, add tables which dynamically adjust this per calibration code from the SCC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: sdhi: Skip bad tapsMarek Vasut2019-11-272-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | Some of the tuning taps produce suboptimal results. Add code which skips those "bad" taps. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: sdhi: Add SCC error checkingMarek Vasut2019-11-271-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | Check SCC for errors after check command if applicable and optionally adjust the bus skew settings accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: sdhi: Disable auto-retuning in HS400Marek Vasut2019-11-271-5/+3
| | | | | | | | | | | | | | | | | | | | | Disable the auto-retuning in HS400 mode in favor of manual calibration. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: sdhi: Adjust HS400 calibration offsetsMarek Vasut2019-11-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Adjust the TMPPORT3 offsets according to the latest information from the chip vendor. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: sdhi: Adjust DT2FF settings for HS400 modeMarek Vasut2019-11-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Adjust the DT2FF offsets in HS400 according to latest information from the chip vendor. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: sdhi: Use 4 tuning taps on M3W up to ES1.2Marek Vasut2019-11-271-3/+6
| | | | | | | | | | | | | | | | | | | | | The M3W up to ES1.2 uses 4 tuning taps for HS400, make it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: sdhi: Track SMPCMP valu in private dataMarek Vasut2019-11-272-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | Retain the SMPCMP value from last calibration in private data. This will be later used for skipping bad taps. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: sdhi: Track current tap number in private dataMarek Vasut2019-11-272-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | Retain the tap number from last calibration in private data. This will be later used for SCC error checking after each command. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mpc83xx: remove unused clock.hYangbo Lu2019-11-271-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The clock.h was to define mxc_get_clock() providing clock value to fsl_esdhc driver. Since fsl_esdhc driver is using global data gd->arch.sdhc_clk directly now, we can remove this file. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: drop eSDHC clock getting in mxc_get_clock() for layerscapeYangbo Lu2019-11-275-35/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although layerscape platforms reuse mxc_get_clock() of i.MX platforms, eSDHC clock getting do not have to use it. It uses global data gd->arch.sdhc_clk directly in fsl_esdhc driver. Even there are more than one eSDHC controllers on SoC, they use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | arm: ls1021a: drop redundant board_mmc_init()Yangbo Lu2019-11-273-43/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The board_mmc_init() defined in board files is actually doing same thing with the cpu_mmc_init() defined in arch/arm/cpu/armv7/ls102xa/cpu.c. So drop it. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | mmc: fsl_esdhc: get clock directly from global dataYangbo Lu2019-11-271-30/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to get clock directly from global data. - Remove uclass clk api method. This was what i.MX platforms were using, while QorIQ platforms weren't. - Get clock only from global data, dropping mxc_get_clock(). QorIQ eSDHC controllers on one silicon use same reference clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | mmc: sdhci: make sdhci_get_cd staticBaruch Siach2019-11-271-1/+1
| | | | | | | | | | | | | | | | | | | | | sdhci_get_cd() is not referenced anywhere else. Limit its scope to sdhci.c. Signed-off-by: Baruch Siach <baruch@tkos.co.il>
* | | Merge tag 'u-boot-stm32-20191126' of ↵Tom Rini2019-11-2838-538/+1014
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Solve warning for stih410-b2260 - Device tree alignment on v5.4-rc4 for all stm32 boards - Correct the eMMC pin configuration on stm32mp157c-ev1 - Add DFU and SPI-NAND support for stm32mp1 board
| * | | stm32mp1: add support for virtual partition readPatrick Delaunay2019-11-264-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add read for OTP and PMIC NVM with alternates on virtual DFU device. Serie-cc: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | stm32mp1: board: add spi nand supportPatrick Delaunay2019-11-262-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the support of the spi nand device in mtdparts command and in dfu_alt_info. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | stm32mp1: configs: activate CONFIG_MTD_SPI_NANDPatrick Delaunay2019-11-263-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Activate the support of SPI NAND in stm32mp1 U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | stm32mp1: activate SET_DFU_ALT_INFOPatrick Delaunay2019-11-263-0/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generate automatically dfu_alt_info for the supported device. The simple command "dfu 0" allows to start the dfu stack on usb 0 for the supported devices: - dfu mtd for nand0 - dfu mtd for nor0 - dfu mmc for SDCard - dfu mmc for eMMC - dfu ram for images in DDR The DUF alternate use the "part", "partubi" and "mmcpart" options to select the correct MTD or GPT partition or the eMMC hw boot partition. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | stm32mp1: activate DFU support and command MTDPatrick Delaunay2019-11-263-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of DFU for MMC, MTD, RAM and MTD command. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | ARM: dts: stm32: update eMMC configuration for stm32mp157c-ev1Patrick Delaunay2019-11-264-8/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the sdmmc2 node for eMMC support on eval board stm32mp157c-ev1. - update slew-rate for pin configuration - update "vqmmc-supply" - remove "st,sig-dir" - add mandatory "pinctrl-names" - add "mmc-ddr-3_3v" This patch solve the eMMC detection issue for command "mmc dev 1". Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | ARM: dts: stm32: DT alignment with kernel v5.4-rc4Patrick Delaunay2019-11-2612-15/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Device tree and binding alignment with kernel v5.4-rc4 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | ARM: dts: stm32: DT alignment with kernel v5.3Patrick Delaunay2019-11-2622-511/+377
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Device tree and binding alignment with kernel v5.3 and converted to SPDX. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
| * | | configs: stih410-b2260: Enable DM_ETH flagPatrice Chotard2019-11-261-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows to fix the following compilation warning: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xxTom Rini2019-11-2859-0/+109
|\ \ \ | |/ / |/| | | | | | | | | | | - powerpc: Fix DM_MMC related build warnings by adding eSDHC device module support for T4240RDB, T2080RDB, T1042D4RDB, T1024RDB, P5040DS, P4080DS, P3041DS, P2041RDB, P2020RDB, P1020RDB platforms
| * | configs: enable eSDHC device module for T4240RDB boardYinbo Zhu2019-11-252-0/+2
| | | | | | | | | | | | | | | | | | | | | Enable eSDHC device module for T4240RDB board Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: enable eSDHC device module for T2080RDB boardYinbo Zhu2019-11-254-0/+4
| | | | | | | | | | | | | | | | | | | | | Enable eSDHC device module for T2080RDB board Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | configs: enable eSDHC device module for T1042D4RDB boardYinbo Zhu2019-11-254-0/+4
| | | | | | | | | | | | | | | | | | | | | Enable eSDHC device module for T1042D4RDB board Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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