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* configs: Enable SPL_FSL_PBL for some LayerScape platformsAlison Wang2019-12-2621-2/+26
| | | | | | | | | | | In commit <db4080d56dec>, SPL_FSL_PBL is removed from the configs of some LayerScape platforms. Actually, SPL_FSL_PBL is needed for SD/NAND boot on LS1021A/LS1043A/LS1046A to create boot binary having SPL binary in PBI format concatenated with u-boot binary. SPL_FRAMEWORK is used on these platforms too. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* ls1028a: Configure stream IDs for integrated PCI and fix up Linux DTAlex Marginean2019-12-264-0/+119
| | | | | | | | | | | Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* arm64: lx2160a: dts: Fix UART node statusVabhav Sharma2019-12-261-0/+2
| | | | | | | | | | LX2160A PL011 UART driver fetch IP block values using platform data from board file instead of device tree. Modified UART nodes in device tree to disable state. Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: Add workaround for USB erratum A-050106Ran Wang2019-12-263-1/+26
| | | | | | | | | | USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar to erratum A-009007, but this one is for LX2160A, and the register value is different. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: fix SPL multi DTB loadingMichael Walle2019-12-261-1/+1
| | | | | | | | Mark board_fit_config_name_match() as weak so a board can overwrite the empty function. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: fsl-layerscape: Increase mmc read size for secure-boot headersUdit Agarwal2019-12-263-17/+17
| | | | | | | | | | | Maximum size of secure boot header to be read from MMC is 12KB which spans across 0x20 blocks. Hence increase the mmc read size for secure boot headers from MMC to 0x20 blocks. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* drivers/fsl-mc: Support DPSPARSER object and apply spb commandFlorinel Iordache2019-12-266-23/+620
| | | | | | | | | | Add support for DPSPARSER object (create/destroy, open/close, apply spb) which is required to configure Soft Parser by using MC. Also add uboot command to apply Soft Parser Blob with command: fsl_mc apply spb <spb_load_addr> Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into nextTom Rini2019-12-24130-36/+254
|\ | | | | | | | | | | | | - Enable DM driver on ppc/km boards - Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x, T104x, P4080, P2041, P2020, P1020, P3041 - Some updates in mpc85xx-ddr driver, km boards
| * ppc/km: enable DM driver support in all defconfigsHolger Brunck2019-12-2310-0/+20
| | | | | | | | | | | | | | | | | | | | | | This is the first step to use DM support for the KM powerpc boards. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> CC: Mario Six <mario.six@gdsys.cc> CC: Wolfgang Denk <wd@denx.de> CC: Valentin Longchamp <valentin.longchamp@ch.abb.com> CC: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: P5040: enable CONFIG_DM_USB supportRan Wang2019-12-234-0/+4
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: powerpc: add usb nodes to P5040 dtsRan Wang2019-12-231-0/+12
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: T4240: enable CONFIG_DM_USB supportRan Wang2019-12-236-0/+6
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: powerpc: add usb nodes to T4240 dtsRan Wang2019-12-231-0/+12
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: T208x: enable CONFIG_DM_USB supportRan Wang2019-12-2310-0/+10
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: T104x: enable CONFIG_DM_USB supportRan Wang2019-12-2319-0/+19
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: powerpc: add usb nodes to T104x dtsRan Wang2019-12-231-0/+12
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: T102x: enable CONFIG_DM_USB supportRan Wang2019-12-2313-0/+13
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * powerpc: add usb nodes to T102x dtsRan Wang2019-12-231-0/+12
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: P4080: enable CONFIG_DM_USB supportRan Wang2019-12-234-0/+4
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: powerpc: add usb nodes to P4080 dtsRan Wang2019-12-231-0/+12
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: P2041: enable CONFIG_DM_USB supportRan Wang2019-12-235-0/+5
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: powerpc: add usb node to p2041 dtsRan Wang2019-12-231-0/+12
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: P2020: enable CONFIG_DM_USB supportRan Wang2019-12-238-0/+8
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: powerpc: add usb node to p2020 dtsRan Wang2019-12-231-0/+6
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: p1020: enable CONFIG_DM_USB supportRan Wang2019-12-2320-0/+20
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: powerpc: add usb nodes to P1020 dtsRan Wang2019-12-231-0/+13
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: p3041ds: enable CONFIG_DM_USB supportRan Wang2019-12-235-0/+5
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arch: powerpc: add usb node in p3041 dtsRan Wang2019-12-231-0/+12
| | | | | | | | | | Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * mpc85xx: ddr: Always start DDR RAM in Self Refresh modeJoakim Tjernlund2019-12-231-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Some of t1042 boards fails DDR init with an Automatic calibration error every now and then. Investigations revealed that true Warm boots never failed. Warm boots has some extra steps performed, one being to start DDRC in Self Refresh and then clearing SR right after. Applying this SR method unconditionally made all our boards stable again, regardless of Cold/Warm boot. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * ppc/kmeter1: remove unused defineHolger Brunck2019-12-231-5/+0
| | | | | | | | | | | | | | | | | | CONFIG_CONS_INDEX is nowhere used for this board, we can drop it. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> CC: Priyanka Jain <priyanka.jain@nxp.com> CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
| * board/km: remove CONFIG_KM_BOARD_NAMEHolger Brunck2019-12-2313-13/+2
| | | | | | | | | | | | | | | | | | | | We can use the existing CONFIG_SYS_CONFIG_NAME define for that and remove the option. Also fix the boot string for all km83xx boards. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> CC: Priyanka Jain <priyanka.jain@nxp.com> CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
| * ppc/km: convert KM_DEF_NETDEV to KconfigHolger Brunck2019-12-239-11/+10
| | | | | | | | | | | | | | | | | | | | Remove this from the board header files and move it to Kconfig. Also use the correct default address for kmtegr1. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> CC: Priyanka Jain <priyanka.jain@nxp.com> CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
| * ppc/km/tegr1: support second localbus clock signalHolger Brunck2019-12-232-0/+19
|/ | | | | | | | | | On kmtegr1 we have to specify the second localbus clock signal also instead of using the default for our ppc 8309 boards. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> CC: Priyanka Jain <priyanka.jain@nxp.com> CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
* Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 ↵Tom Rini2019-12-18223-706/+12370
|\ | | | | | | | | | | | | | | | | | | | | into next - Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral
| * x86: Add chromebook_coralSimon Glass2019-12-1511-0/+1296
| | | | | | | | | | | | | | | | | | Add support for coral which is a range of Apollo Lake-based Chromebook released in 2017. This also includes reef released in 2016, since it is based on the same SoC. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add FSP supportSimon Glass2019-12-153-0/+877
| | | | | | | | | | | | | | | | The memory and silicon init parts of the FSP need support code to work. Add this for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add FSP structuresSimon Glass2019-12-154-0/+440
| | | | | | | | | | | | | | | | These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add Kconfig and MakefileSimon Glass2019-12-153-0/+98
| | | | | | | | | | | | | | Add basic plumbing to allow Apollo Lake support to be used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add P2SB driverSimon Glass2019-12-152-0/+167
| | | | | | | | | | | | | | | | Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add SPL/TPL initSimon Glass2019-12-152-0/+272
| | | | | | | | | | | | | | | | Add code to init the system both in TPL and SPL. Each phase has its own procedure. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add a CPU driverSimon Glass2019-12-155-0/+81
| | | | | | | | | | | | | | Add a bare-bones CPU driver so that CPUs can be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add SPL loadersSimon Glass2019-12-152-0/+180
| | | | | | | | | | | | | | | | Add loaders for SPL and TPL so that the next stage can be loaded from memory-mapped SPI or, failing that, the Fast SPI driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * spl: Add methods to find the position/size of next phaseSimon Glass2019-12-152-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | Binman supports writing the position and size of U-Boot proper and SPL into the previous phase of U-Boot. This allows the next phase to be easily located and loaded. Add functions to return these useful values, along with symbols to allow TPL to load SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add PUNIT driverSimon Glass2019-12-152-0/+97
| | | | | | | | | | | | | | | | Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a syscon driver since it only needs to be probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add PCH driverSimon Glass2019-12-153-0/+46
| | | | | | | | | | | | | | | | Add a driver for the Apollo Lake Platform Controller Hub. It does not have any functionality and is just a placeholder for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add LPC driverSimon Glass2019-12-153-0/+205
| | | | | | | | | | | | | | | | | | This driver the LPC and provides a few functions to set up LPC features. These should probably use ioctls() or perhaps, better, have specific uclass methods. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add ITSS driverSimon Glass2019-12-153-0/+258
| | | | | | | | | | | | | | | | | | This driver models some sort of interrupt thingy but there are so many abreviations that I cannot find out what it stands for. Possibly something to do with interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add hostbridge driverSimon Glass2019-12-152-0/+180
| | | | | | | | | | | | | | | | This driver models the hostbridge as a northbridge. It simply sets up the graphics BAR. It supports of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: apl: Add systemagent driverSimon Glass2019-12-153-0/+62
| | | | | | | | | | | | | | | | This driver handles communication with the systemagent which needs to be told when U-Boot has completed its init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * i2c: designware: Add Apollo Lake supportSimon Glass2019-12-151-0/+25
| | | | | | | | | | | | | | | | | | For Apollo Lake we need to take the I2C bus controller out of reset before using this. Add this functionality to the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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