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* treewide: Move CONFIG_PHY_MARVELL to KconfigMario Six2018-05-14210-19/+192
| | | | | | | | | | | The CONFIG_PHY_MARVELL has already been migrated to Kconfig (some boards already had it in their Kconfig), but had not been moved for older boards. Move it to the defconfigs for all boards. Signed-off-by: Mario Six <mario.six@gdsys.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-rockchipTom Rini2018-05-142-0/+12
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| * rockchip: clk: rk3288: handle clk_enable requests for GMACJonathan Gray2018-05-141-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since b0ba1e7e9d9b9441a18048ec67a3b3100c096975 (rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC) Ethernet no longer probes on RK3288. Add no-ops for GMAC clocks observed to be requested which match the clk_enable cases in RK3368 and RK3399. Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: Wadim Egorov <w.egorov@phytec.de> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: set SYS_NS16550_MEM32 for all SoCsJonathan Gray2018-05-141-0/+2
|/ | | | | | | | | | | | | | | | Add back part of patch send out as 'rockchip: enable SYS_NS16550 for all SoCs by default' that seems to have gotten lost when it got merged to set SYS_NS16550_MEM32. Allows serial output to work on tinker-rk3288 again after c3c0331db1fb7b1f4ff41e144fc04353b37c785c. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* Merge git://git.denx.de/u-boot-marvellTom Rini2018-05-1489-6283/+9734
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| * phy: marvell: a3700: Fix compatible string for ehciMarek Behún2018-05-141-1/+1
| | | | | | | | | | | | | | | | The DTS file for armada-37xx uses the string "marvell,armada3700-ehci", but the code searched for "marvell,armada-3700-ehci". Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: a38x: use non-zero size for ddr scrubbingChris Packham2018-05-143-1/+5
| | | | | | | | | | | | | | | | Make ddr3_calc_mem_cs_size() global scope and use it in ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: a38x: restore support for setting timingChris Packham2018-05-149-11/+29
| | | | | | | | | | | | | | | | | | | | This restores support for configuring the timing mode based on the ddr_topology. This was originally implemented in commit 90bcc3d38d2b ("driver/ddr: Add support for setting timing in hws_topology_map") but was removed as part of the upstream sync. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: a38x: sync ddr training code with upstreamChris Packham2018-05-1456-5139/+7944
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: a38x: remove some unused codeChris Packham2018-05-147-794/+0
| | | | | | | | | | | | | | | | | | No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to remove unused sections in the rest of the ddr/marvell/a38x code. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: a38x: move sys_env_device_rev_getChris Packham2018-05-143-27/+24
| | | | | | | | | | | | | | | | | | | | Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESSChris Packham2018-05-142-2/+1
| | | | | | | | | | | | | | | | | | | | | | PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite only being used in the serdes code. Move this definition to ctrl_pex.h where all the other PEX defines are. Also remove the duplicate definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in ctrl_pex.h. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm64: mvebu: Add basic support for the Turris Mox boardMarek Behún2018-05-149-1/+463
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic support for the Turris Mox board from CZ.NIC, which is currently being crowdfunded on Indiegogo. Turris Mox is as modular router based on the Armada 3720 SOC (same as EspressoBin). The basic module can be extended by different modules. The device tree binary for the kernel can be dependent on which modules are connected, and in what order. Because of this, the board specific code creates in U-Boot a variable called module_topology, which carries this information. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * watchdog: Add support for Armada 37xx CPU watchdogMarek Behún2018-05-144-0/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the CPU watchdog found on Marvell Armada 37xx SoCs. There are 4 counters which can be set as CPU watchdog counters. This driver uses the second counter (ID 1, counting from 0) (Marvell's Linux also uses second counter by default). In the future it could be adapted to use other counters, with definition in the device tree. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * net: mvneta: Fix fault when wrong device treeMarek Behún2018-05-141-0/+4
| | | | | | | | | | | | | | | | | | | | The driver does not check id phy_connect failed (for example on wrong property name in device tree). In such a case a fault occurs and the CPU is restarted. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: core: Cosmetic fixesMarek Behún2018-05-142-53/+52
| | | | | | | | | | | | | | | | | | Move the reg_set* functions into comphy.h as static inline functions. Change return type of get_*_string to const char *. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * clk: armada-37xx: Support soc_clk_dumpMarek Behún2018-05-142-1/+37
| | | | | | | | | | | | | | | | Add support for the clk dump command on Armada 37xx. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * spi: mvebu_a3700_spi: Use Armada 37xx clk driver for SPI clock frequencyMarek Behún2018-05-145-26/+37
| | | | | | | | | | | | | | | | | | | | | | | | Since now we have driver for clocks on Armada 37xx, use it to determine SQF clock frequency for the SPI driver. Also change the default config files for Armada 37xx devices so that the clock driver is enabled by default, otherwise the SPI driver cannot be enabled. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * driver: clk: Add support for clocks on Armada 37xxMarek Behún2018-05-147-0/+651
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Save/restore selector reg in SGMII initMarek Behún2018-05-142-2/+8
| | | | | | | | | | | | | | | | | | | | | | In SGMII initialization PIN_PIPE_SEL has to be zero when resetting the PHY. Since comphy_mux already set the selector register to correct values, we have to store it's value before setting it to 0 and restore it after SGMII init. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Use comphy_mux on Armada 37xx.Marek Behún2018-05-142-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lane 0 supports SGMII1 and USB3. Lane 1 supports SGMII0 and PEX0. Lane 2 supports SATA0 and USB3. This is needed for Armada 37xx. This introduces new device tree bindings. AFAIK there is currently no driver for Armada 37xx comphy in Linux. When such a driver will be pushed into Linux, this will need to be rewritten accordingly. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Fix SGMII cfg and stat register addressesMarek Behún2018-05-141-2/+2
| | | | | | | | | | | | | | | | The register addresses on lanes 0 and 1 are switched, first comes 1 and then 0. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: mux: Support nontrivial node order in selector registerMarek Behún2018-05-143-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently comphy_mux supports only trivial order of nodes in pin selector register, that is lane N on position N*bitcount. Add support for nontrivial order, with map stored in device tree property mux-lane-order. This is needed for Armada 37xx. As far as I know, there is no driver for Armada 37xx comphy in the kernel. When such a driver comes, this will need to be rewritten to support the device tree bindings from the kernel. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: revise the USB3 comphy setting during power onzachary2018-05-142-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is based on commit d9899826 by zachary <zhangzg@marvell.com> from u-boot-marvell, see github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/d9899826 - According to design specification, the transmitter should be set to high impedence mode during electrical idle. Thus transmitter should detect RX at high impedence mode also, and delay is needed to accommodate high impedence off latency. Otherwise the USB3 will have detection issue that most of the time the USB3 device can not be detected at all, or be detected as USB2 device sometimes. Modified registers: RD005C302h (R181h) (0051h) Lane Configuration 1 Bit 6: set to 1 to let Tx detect Rx at HiZ mode Bit [3:4]: set to 2 to be delayed by 2 clock cycles Bit 0: set to 1 to set transmitter to high impedance mode during idle. - USB3 De-emphasize level of -3.5dB is mandatory, but USB3 MAC selects 0x2 (emphasize disabled) in the MAC_PHY_TXDEEMPH [1:0], while it is supposed to select 0x1(3.5dB emphasize). Thus need to override what comes from the MAC(by setting register 0x1c2 bit2 to 0x1) and to configure the overridded values of MAC_PHY_TXDEEMPH [1:0] to 0x1(bit15 of register 0x181 and bit0 of register 0x180). - According to USB3 application note, need to update below comphy registers: Set max speed generation to USB3.0 5Gbps(set RD005C04Ah bit[11:10] to 1) Set capacitor value to 0xF(set RF005C224 bit[3:0] to 0xF) Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Set USB3 RX wait depending on ref clockMarek Behún2018-05-141-5/+3
| | | | | | | | | | | | | | | | | | | | | | According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7 when reference clock is at 25 MHz. The specification (at least the version I have) does not mentoin the setting for 40 MHz reference clock, but Marvell's U-Boot sets 0xC in that case. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Access USB3 register indirectly on lane 2Marek Behún2018-05-142-35/+68
| | | | | | | | | | | | | | | | | | | | When USB3 is on comphy lane 2 on the Armada 37xx, the registers have to be accessed indirectly via SATA indirect access. This is the case of the Turris Mox board from CZ.NIC. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Use reg_set_indirect istead of 2 reg_setsMarek Behún2018-05-141-12/+20
| | | | | | | | | | | | | | | | | | Create a special function for indirect register setting, reg_set_indirect, and use it instead of the two calls to reg_set. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Use (!ret) instead of (ret == 0)Marek Behún2018-05-141-13/+13
| | | | | | | | | | | | | | | | In U-Boot it is usually written this way. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Use same timeout for all register pollingMarek Behún2018-05-141-13/+3
| | | | | | | | | | | | | | | | | | The timeout is set to PLL_LOCK_TIMEOUT in every call to comphy_poll_reg. Remove this parameter from the function. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Don't create functional macro for each registerMarek Behún2018-05-142-111/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there is for each register special functional macro, ie: LANE_CFG1_ADDR(u) GLOB_CLK_SRC_LO_ADDR(u) ... where can be either PCIE or USB3. Change this to one function PHY_ADDR(unit, addr). The code becomes: phy_addr(PCIE, LANE_CFG1) phy_addr(PCIE, GLOB_CLK_SRC_LO) ... Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Use reg_set16 instead of phy_write16Marek Behún2018-05-142-18/+22
| | | | | | | | | | | | | | | | | | The macro phy_write16 is not used by the rest of the code, phy_read16 is not used at all. We also change the macro SGMIIPHY_ADDR to a static inline function. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
| * phy: marvell: a3700: Change return type of macro MVEBU_REGMarek Behún2018-05-142-118/+96
|/ | | | | | | | | All the calls to reg_set and friends have to cast the first argument to void __iomem *. Lets change the return type of the MVEBU_REG macro instead. Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
* mmc: Improve tinificationMarek Vasut2018-05-132-26/+59
| | | | | | | | | | | | | | | | | Drop all the extra content from the MMC core, so that tiny MMC support is really tiny, no fancy anything. That means the tiny MMC support does only 1-bit transfers at default speed settings. Moreover, this patch drops duplicate instance of struct mmc mmc_static, which wasted about 360 bytes. Furthermore, since MMC tiny supports only one controller at all times, get rid of mallocating the ext csd backup and replace it with static array. All in all, this patch saves ~4 kiB of bloat from the MMC core, which on platforms with severe limitations can be beneficial. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup checkpatch.pl style warnings] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-tegraTom Rini2018-05-1116-157/+356
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| * apalis_t30: fix optional pcie port reset for reliable pcie operationMarcel Ziswiler2018-05-102-1/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | Allow optionally bringing up the Apalis type specific 4 lane PCIe port as well as the PCIe switch as found on the Apalis Evaluation board. In order to avoid violating the PCIe reset timing do this by overriding the tegra_pcie_board_port_reset() function. Note however that both the Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe port are also left disabled in the device tree by default. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * apalis_t30: fix pcie port 0 and 1 pin muxingMarcel Ziswiler2018-05-101-7/+9
| | | | | | | | | | | | | | | | Fix optional Apalis type specific 4 lane PCIe port 0 and Apalis PCIe port 1 pin muxing. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * apalis_t30: describe pcie portsMarcel Ziswiler2018-05-101-0/+3
| | | | | | | | | | | | | | Add some more comments describing the various PCIe ports available. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * apalis-tk1: fix pcie reset for reliable gigabit ethernet operationMarcel Ziswiler2018-05-102-95/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that the current PCIe reset implementation in the PCIe board init function is not quite working reliably due to PCIe reset timing violations. Fix this by overriding the tegra_pcie_board_port_reset() function. Also allow optionally bringing up the PCIe switch as found on the Apalis Evaluation board. Note however that the Apalis PCIe port is also left disabled in the device tree by default. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * power: as3722: add as3722_ldo_set_voltage signature to header fileMarcel Ziswiler2018-05-101-0/+1
| | | | | | | | | | | | | | | | | | | | Just like the already present as3722_sd_set_voltage() add the currently missing signature of the as3722_ldo_set_voltage() function to its header file. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * pci: tegra: introduce weak tegra_pcie_board_port_reset() functionMarcel Ziswiler2018-05-102-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a weak tegra_pcie_board_port_reset() function by default calling the existing tegra_pcie_port_reset() function. Additionally add a tegra_pcie_port_index_of_port() function to retrieve the specific PCIe port index if required. This allows overriding the PCIe port reset functionality from board specific code as e.g. required for Apalis T30 and Apalis TK1. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * power: as3722: fix ldo_get/set_enable for ldo index bigger than 7Marcel Ziswiler2018-05-102-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | Fix ldo_get_enable() and ldo_set_enable() functions for LDOs with an index > 7. Turns out there are actually two separate AS3722_LDO_CONTROL registers AS3722_LDO_CONTROL0 and AS3722_LDO_CONTROL1. Actually make use of both. While at it also actually use the enable parameter of the ldo_set_enable() function which now truly allows disabling as opposed to only enabling LDOs. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * apalis-tk1: add missing as3722 gpio0 configurationMarcel Ziswiler2018-05-101-3/+3
| | | | | | | | | | | | | | | | | | As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module explicitly configure it to high-impedance as well. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * configs: apalis-tk1: fix boot failure using ext4 rootfsSanchayan Maity2018-05-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | Trying to boot from an ext4 rootfs fails due to us defaulting to ext3. While the downstream T20/T30 L4T kernel has issues with ext4 later TK1 L4T should work just fine with it. Hence enable ext4 for sdboot and usbboot on TK1. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * configs: colibri_t20: enable mtdMarcel Ziswiler2018-05-101-0/+1
| | | | | | | | | | | | | | Enable CONFIG_MTD as well to make sure UCLASS_MTD is available Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * configs: harmony: enable live tree, mtd and ubiMarcel Ziswiler2018-05-102-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot on Harmony recently got broken by ongoing driver model resp. live tree migration work: U-Boot 2018.03-rc3 (Feb 21 2018 - 15:43:08 +0100) TEGRA20 Model: NVIDIA Tegra20 Harmony evaluation board Board: NVIDIA Harmony DRAM: 1 GiB Video device 'dc@54200000' cannot allocate frame buffer memory -ensure the device is set up before relocation Error binding driver 'tegra_lcd': -28 Some drivers failed to bind Error binding driver 'generic_simple_bus': -28 Some drivers failed to bind initcall sequence 3ffa86d0 failed at call 00121dc0 (err=-28) This commit fixes this by enabling live tree, MTD and UBI for Harmony as well. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * mtd: nand: tegra: convert to driver model and live treeMarcel Ziswiler2018-05-101-43/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra NAND driver recently got broken by ongoing driver model resp. live tree migration work: NAND: Could not decode nand-flash in device tree Tegra NAND init failed 0 MiB A patch for NAND uclass support was proposed about a year ago: https://patchwork.ozlabs.org/patch/722282/ It was not merged and I do not see on-going work for this. This commit just provides a driver model probe hook to retrieve further configuration from the live device tree. As there is no NAND ulass as of yet (ab)using UCLASS_MTD. Once UCLASS_NAND is supported, it would be possible to migrate to it. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | SPDX: Correct SPDX tags from recent xilinx mergeTom Rini2018-05-113-6/+3
| | | | | | | | | | | | | | Correct the SPDX tag format. Fixes: 3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze") Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblazeTom Rini2018-05-1185-314/+3176
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup
| * | arm64: zynqmp: Enable UHS support for ZCU102 Rev1.0 boardSiva Durga Prasad Paladugu2018-05-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables UHS support for ZynqMP zcu102 rev 1.0 board. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | mmc: zynq_sdhci: Add support for SD3.0Siva Durga Prasad Paladugu2018-05-114-5/+476
| | | | | | | | | | | | | | | | | | | | | This patch adds support of SD3.0 for ZynqMP. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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