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* Merge tag 'u-boot-rockchip-20191026' of ↵WIP/26Oct2019Tom Rini2019-10-2648-158/+2034
|\ | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Add support for rockchip pmic rk805,rk809, rk816, rk817 - Add rk3399 board Leez support - Fix bug in rk3328 ram driver - Adapt SPL to support ATF bl31 with entry at 0x40000
| * rockchip: firefly-rk3288: Enable TPL supportKever Yang2019-10-262-3/+3
| | | | | | | | | | | | | | This patch enable TPL support for firefly-rk3288 board, which works ths same way with other RK3288 board like Tinker, evb. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: adding the missing "/" in entries of boot_devicesLevin Du2019-10-265-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work as expected. When board_boot_order() `spl-boot-order.c` meets "same-as-spl", it gets the conf by looking the boot_devices table by boot source, and parse the node by the conf with: node = fdt_path_offset(blob, conf); which will failed without the "/" indicating the path. Currently only entries of boot_devices in rk3399 have the "/" prefix. Therefore add the missing ones in other boards. Signed-off-by: Levin Du <djw@t-chip.com.cn> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: config: update CONFIG_SPL_MAX_SIZE for 64bit CPUsKever Yang2019-10-263-3/+3
| | | | | | | | | | | | | | | | | | | | Since we move the ATF bl31 entry for 64bit CPUs to 0x40000, we need to limit the SPL size in 0x40000(start from 0) so that we don't need to do the relocate for ATF loading. Note that there will be separate BSS, STACK and MALLOC heap, so the size 0x40000(256KB) should be enough for SPL text. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: update SPL_STACK_R_ADDRKever Yang2019-10-2618-17/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config; default to 0x4000000(64MB) instead of 0x80000(512KB) for this address can support all the SoCs including those may have only 64MB memory, and also reserve enough space for atf, kernel(in falcon mode) loading. After the ATF entry move to 0x40000, the stack from 0x80000 may be override when loading ATF bl31. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: evb-px5: defconfig: no need to reserve IRAM for SPLKever Yang2019-10-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3328: defconfig: no need to reserve IRAM for SPLKever Yang2019-10-262-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: defconfig: no need to reserve IRAM for SPLKever Yang2019-10-2613-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code, and when we introduce the TPL, the SPL space is in DRAM, we reserve space to avoid SPL text overlap with ATF bl31. Now we decide to move ATF entry point to 0x40000 instead of 0x1000, so that the SPL can have 0x4000 as code size and no need to reserve space or relocate before loading ATF. The mainline ATF has update since: 0aad563c rockchip: Update BL31_BASE to 0x40000 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * common: spl: atf: support booting bl32 imageJoseph Chen2019-10-261-14/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trusted-Firmware can also initialize a secure payload to use as a trusted execution environment. In general for the arm64 case this is provided as separate image and uboot is supposed to also place it in a predetermined location in memory and add the necessary parameters to the ATF boot params. So add the possibility to get this tee payload from the provided FIT image and setup things as necessary. Tested on a Rockchip PX30 with mainline TF-A, mainline OP-Tee (with pending PX30 support) and mainline 5.4-rc1 Linux kernel. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: make_fit_atf.py: allow inclusion of a tee binaryHeiko Stuebner2019-10-261-6/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A trusted execution environment should also get loaded as loadable from a fit image, so add the possibility to present a tee.elf to make_fit_atf.py that then gets included as additional loadable into the generated its. For ease of integration the additional loadable is created as atf_(x+1) after all others to re-use core generation loops. Tested against the combinations of 1-part-atf and multi-part-atf each time with and without a tee binary present. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * ram: rk3328: Fix loading of skew valuesSimon South2019-10-261-1/+1
| | | | | | | | | | | | | | | | Fix a typo that caused incorrect values to be loaded into the DRAM controller's deskew registers. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * ram: rk3328: Use correct frequency units in functionSimon South2019-10-261-2/+2
| | | | | | | | | | | | | | | | | | Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: dts: rk3328: rock64: Add same-as-spl orderEmmanuel Vadot2019-10-261-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | rk3328 can use same-as-spl option so next loaders are loaded from the same medium. Add the boot order in the rock64 dts otherwise booting from sdcard will result in u-boot looking into the eMMC. Signed-off-by: Emmanuel Vadot <manu@freebsd.org> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * clk: rockchip: rk3328: Configure CPU clockSimon South2019-10-262-0/+5
| | | | | | | | | | | | | | | | Add a call to rk3328_configure_cpu() during initialization to set the CPU-clock frequency. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * rockchip: rk3399: Add Leez P710 supportAndy Yan2019-10-265-0/+723
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specification - Rockchip RK3399 - LPDDR4 - TF sd scard slot - eMMC - M.2 B-Key for 4G LTE - AP6256 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 - TYPE-C Power supply Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1: "arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC" (sha1: fc702ed49a8668a17343811ee28214d845bfc5e6) Signed-off-by: Andy Yan <anyshrk@gmail.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * power: pmic: rk809: support rk809 pmicJoseph Chen2019-10-263-2/+74
| | | | | | | | | | | | | | | | | | | | | | | | The RK809 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(5*BUCKs, 9*LDOs, 2*SWITCHs) - RTC - Clocking Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * power: pmic: rk817: support rk817 pmicJoseph Chen2019-10-263-7/+297
| | | | | | | | | | | | | | | | | | | | | | | | The RK817 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 1* BOOST, 9*LDOs, 1*SWITCH) - RTC - Clocking Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * power: pmic: rk805: support rk805 pmicElaine Zhang2019-10-263-0/+19
| | | | | | | | | | | | | | | | | | | | | | The RK805 are a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 3*LDOs) - RTC - Clocking Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * power: pmic: rk816: support rk816 pmicElaine Zhang2019-10-263-6/+136
| | | | | | | | | | | | | | | | | | | | | | The RK816 is a Power Management IC (PMIC) for multimedia and handheld devices. They contains the following components: - Regulators(4*BUCKs, 1*BOOST, 6*LDOs, 1*SWITCH) - RTC - Clocking Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * power: regulator: rk8xx: update the driver for rk808 and rk818Elaine Zhang2019-10-261-82/+465
| | | | | | | | | | | | | | | | | | In order to adapt the following pmics, make the interface more compatible. Support buck and ldo suspend voltage setting and getting. Supprot buck and ldo suspend enable/disable setting and getting. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
| * dm: regulator: support regulator more stateJoseph Chen2019-10-264-0/+218
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | support parse regulator standard property: regulator-off-in-suspend; regulator-init-microvolt; regulator-suspend-microvolt: regulator_get_suspend_enable regulator_set_suspend_enable regulator_get_suspend_value regulator_set_suspend_value Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mipsWIP/25Oct2019Tom Rini2019-10-2575-545/+2327
|\ \ | |/ |/| | | | | | | | | | | | | - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC
| * configs: mtmips: remove configs which are selected in Kconfig or uselessWeijie Gao2019-10-254-28/+0
| | | | | | | | | | | | | | Some configs are selected in Kconfig and is no longer needed in the defconfig files. Some configs (power domain, ram) are never used. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: select essential drivers in KconfigWeijie Gao2019-10-252-0/+8
| | | | | | | | | | | | | | Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the system, they should be always selected. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mips: mtmips: change baudrate table for all boardsWeijie Gao2019-10-252-2/+2
| | | | | | | | | | | | | | This patch changes baudrate table for all boards preparing for using mtk highspeed uart driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add default pinctrl to eth nodes for all boardsWeijie Gao2019-10-252-0/+4
| | | | | | | | | | | | | | | | | | | | | | This patch adds default eth pinctrl for all boards. There are two pinctrl nodes used for two scenarios: ephy_iot_mode - for IOT boards which have only one port (PHY0) ephy_router_mode - For routers which have more than one ports Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add default pinctrl for gardena-smart-gateway-mt7688Weijie Gao2019-10-251-0/+3
| | | | | | | | | | | | | | This adds default pinctrl (dual SPI chip select) for gardena smart gateway Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add mmc related nodes for mt7628an.dtsiWeijie Gao2019-10-251-0/+22
| | | | | | | | | | | | This patch adds mmc related nodes for mt7628an.dtsi Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: add a dts property cd-active-high for builtin-cd modeWeijie Gao2019-10-251-1/+5
| | | | | | | | | | | | | | This patch adds a dts property cd-active-high for builtin-cd mode to make it configurable instead of using hardcoded active-low. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCsWeijie Gao2019-10-252-4/+21
| | | | | | | | | | | | This patch adds mmc support for MediaTek MT7620/MT7628 SoCs. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: enable eth port0 led and link poll functions for all boardsWeijie Gao2019-10-253-1/+27
| | | | | | | | | | | | | | This patch adds default p0led status and phy0 link polling for all boards. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mt7628-eth: add support to isolate LAN/WAN portsWeijie Gao2019-10-251-0/+32
| | | | | | | | | | | | | | This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mt7628-eth: free rx descriptor on receiving failureWeijie Gao2019-10-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor. This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mt7628-eth: make phy link up detection optional via DTWeijie Gao2019-10-252-29/+31
| | | | | | | | | | | | | | | | | | | | | | | | The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy resetWeijie Gao2019-10-251-37/+8
| | | | | | | | | | | | | | | | | | This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao2019-10-252-68/+158
| | | | | | | | | | | | | | | | This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: update reset controller node for mt7628Weijie Gao2019-10-251-12/+24
| | | | | | | | | | | | This patch updates reset controller node for mt7628 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * reset: add reset controller driver for MediaTek MIPS platformWeijie Gao2019-10-254-0/+126
| | | | | | | | | | | | | | This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add default pinctrl for uart nodesWeijie Gao2019-10-251-0/+9
| | | | | | | | | | | | This patch adds default pinctrl for uart nodes Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add pinctrl node for mt7628Weijie Gao2019-10-251-0/+150
| | | | | | | | | | | | This patch adds pinctrl node with default pin state for mt7628an.dtsi. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * pinctrl: add support for MediaTek MT7628Weijie Gao2019-10-257-0/+747
| | | | | | | | | | | | | | This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * spi: mt7621-spi: restore default register value after each xferWeijie Gao2019-10-251-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * spi: mt7621-spi: remove data cache and rewrite its xfer functionWeijie Gao2019-10-251-106/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all. To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order. With this patch, any amount of data can be read/written in a single xfer function call. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * spi: mt7621-spi: use clock frequency from clk driverWeijie Gao2019-10-251-7/+13
| | | | | | | | | | | | | | This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: add clock node for mt7628Weijie Gao2019-10-251-4/+17
| | | | | | | | | | | | | | This patch adds clkctrl node for mt7628 and adds clocks property for some node. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * clk: add clock driver for MediaTek MT76x8 platformWeijie Gao2019-10-254-0/+199
| | | | | | | | | | | | | | | | This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: enable high-speed UART support for mt7628Weijie Gao2019-10-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which support baudrate up to 921600. The high-speed UART is compatible with ns16550 when baudrate <= 115200. Add compatible string to dtsi file so u-boot can use it when serial_mtk driver is built in. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * dts: mtmips: move uart property clock-frequency into mt7628an.dtsiWeijie Gao2019-10-253-2/+6
| | | | | | | | | | | | | | | | The UART of MT7628 has fixed 40MHz input clock so there is no need to put clock-frequency in every dts files. Just put it into the common dtsi file. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * serial: serial_mtk: add non-DM version for SPLWeijie Gao2019-10-252-17/+187
| | | | | | | | | | | | | | | | This patch adds non-DM version for mtk hsuart driver and makes it compatible with ns16550a driver in configuration. This is needed in SPL with CONFIG_SPL_DM disabled for reducing size. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
| * serial: serial_mtk: enable FIFO and disable flow controlWeijie Gao2019-10-251-0/+21
| | | | | | | | | | | | | | This patch adds codes to enable FIFO and disable flow control taken from ns16550 driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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