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* board: ls1043a: use default scan_dev_for_bootMian Yousaf Kaukab2019-03-031-6/+0
| | | | | | | | | Default environment variable is more complete. Also scans for efi binaries for example. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls1043a: enable dhcp bootMian Yousaf Kaukab2019-03-031-1/+2
| | | | | | | | dhcp boot is a useful feature and works out-of-the-box on these platforms. Enable it as a boot source. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls1043a: enable EFI_LOADER_BOUNCE_BUFFERMian Yousaf Kaukab2019-03-0317-0/+17
| | | | | | | | EFI applications need bounce buffers to work properly on these platforms. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls1046a: use default scan_dev_for_bootMian Yousaf Kaukab2019-03-031-7/+0
| | | | | | | | Default environment variable is more complete. Also scans for efi binaries for example. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls1046a: enable dhcp bootMian Yousaf Kaukab2019-03-031-1/+2
| | | | | | | | dhcp boot is a useful feature and works out-of-the-box on these platforms. Enable it as a boot source. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls1046a: enable EFI_LOADER_BOUNCE_BUFFERMian Yousaf Kaukab2019-03-0317-0/+17
| | | | | | | | EFI applications need bounce buffers to work properly on these platforms. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls2080ardb: use default scan_dev_for_bootMian Yousaf Kaukab2019-03-031-12/+0
| | | | | | | | Default environment variable is more complete. Also scans for efi binaries for example. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* Revert "ls2080ardb: remove dhcp function from env as boot source"Mian Yousaf Kaukab2019-03-031-1/+2
| | | | | | | | | | | dhcp boot is a useful feature and works out-of-the-box for ls2088a platforms. Moreover, no solid reason is given for disabling it. Revert the patch to re-enable it. This reverts commit aea5cd75e63c20de4c00ce24a93eeee8542f923e. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls1088ardb: use default scan_dev_for_bootMian Yousaf Kaukab2019-03-031-12/+0
| | | | | | | | Default environment variable is more complete. Also scans for efi binaries for example. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* Revert "ls1088a: remove dhcp function from u-boot env as boot source"Mian Yousaf Kaukab2019-03-031-1/+2
| | | | | | | | | | | dhcp boot is a useful feature and works out-of-the-box for ls1088a platforms. Moreover, no solid reason is given for disabling it. Revert the patch to re-enable it. This reverts commit 863e42e8b1f9e97d87919e20e34a7b98089f7522. Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls1088a: fix fsl-mc search pathMian Yousaf Kaukab2019-03-031-1/+1
| | | | | | | | | | | | Path for fsl-mc node in kernel device-tree is /soc/fsl-mc whereas in u-boot it is /fsl-mc. Fix the incorrect search path to fix following error: fdt_fixup_board_enet: ERROR: fsl-mc node not found in device tree (error -1) Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* board: ls1088a: fix dppa exit when using efi bootMian Yousaf Kaukab2019-03-031-4/+6
| | | | | | | | | Same issue for ls2080a was fixed by following patch: b7b8410a8f ls2080: Exit dpaa only right before exiting U-Boot Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Reviewed-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2019-02-283-1/+62
|\ | | | | | | - SoCFPGA cache/gpio fixes
| * ARM: socfpga: Clear PL310 early in SPLMarek Vasut2019-02-251-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * ARM: socfpga: Configure PL310 latenciesMarek Vasut2019-02-251-0/+3
| | | | | | | | | | | | | | | | | | Configure the PL310 tag and data latency registers, which slightly improves performance and aligns the behavior with Linux. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
| * ARM: cache: Fix incorrect bitwise operationMarek Vasut2019-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The loop implemented in the code is supposed to check whether the PL310 operation register has any bit from the mask set. Currently, the code checks whether the PL310 operation register has any bit set AND whether the mask is non-zero, which is incorrect. Fix the conditional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Tom Rini <trini@konsulko.com> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot")
| * gpio: altera_pio: fix get_valueJulien Béraud2019-02-251-1/+1
| | | | | | | | | | | | | | gpio_get_value should return 0 or 1, not the value of bit & (1 << pin) Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2019-02-2817-37/+32
|\ \ | | | | | | | | | - Gen2/Gen3 fixes for warnings and sdhi
| * | mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8Marek Vasut2019-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to latest specification rev.0026 and after confirmation with HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on H3 ES2.0 SoC. Make it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: tmio: Clear BUSWIDTH bit when WMODE bit is setMarek Vasut2019-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to latest specification rev.0026, when HOST_MODE bit 0 (WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear HOST_MODE bit 8 in such case and align the code with Linux and avoid possible unforeseen issues. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: rmobile: Convert Gen2 to OF_SEPARATEMarek Vasut2019-02-258-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | Convert R-Car Gen2 from OF_EMBED to OF_SEPARATE, thus getting rid of one of the deprecation warnings. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Sync Gen3 defconfigsMarek Vasut2019-02-253-3/+0
| | | | | | | | | | | | | | | | | | | | | Synchronize Gen3 defconfigs in wake of the Kconfig option changes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Imply SoC per boardMarek Vasut2019-02-251-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | Imply all SoCs supported by a given board. This allows building single U-Boot binary for boards which can have multiple SoCs. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | pinctrl: renesas: Drop def_bool per SoCMarek Vasut2019-02-251-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | Drop per SoC def_bool on each driver, since this is now implied by SoC Kconfig option instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | clk: rmobile: Drop def_bool per SoCMarek Vasut2019-02-251-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | Drop per SoC def_bool on each driver, since this is now implied by SoC Kconfig option instead. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Imply pinctrl drivers per SoCMarek Vasut2019-02-252-0/+10
| | | | | | | | | | | | | | | | | | | | | Imply preferred pin control driver per SoC, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | ARM: rmobile: Imply clock drivers per SoCMarek Vasut2019-02-252-0/+10
| |/ | | | | | | | | | | | | Imply preferred clock driver per SoC, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2019-02-286-193/+285
|\ \ | | | | | | | | | - Various Bananapi fixes
| * | sunxi: Add Bananapi M2+ H5 boardChen-Yu Tsai2019-02-183-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the H5 is pin compatible with the H3, vendors tend to upgrade their existing H3 products with an H5 SoC swap. This is the case with the Bananapi M2+ H5. Add the following to support it: - device tree file: synced from Linux v5.0-rc1, - defconfig: copy of bananapi_m2_plus_h3_defconfig with only SoC family and default device tree file name changed - MAINTAINERS entry Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: Rename Sinovoip BPI M2 Plus to Bananapi M2 Plus H3Chen-Yu Tsai2019-02-182-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The brand Sinovoip is used for Sinovoip's original VOIP products, while the Bananapi brand is for the single board computers they produce. This has been verified by Bananapi. Rename the board from "Sinovoip BPI M2 Plus" to "Bananapi M2 Plus". For the defconfig file, all lowercase is used. To support the H5 variant of this board, the "H3" suffix is added to the defconfig name. Also add myself as one of the board maintainers. As the device tree files were already correctly named, they do not require any changes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> [jagan: removed unneeded message from commit body] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * | sunxi: Sync Bananapi M2+ device tree from Linux v5.0-rc1Chen-Yu Tsai2019-02-182-188/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of commit aa8fee415f46 ("ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2 Plus") in the Linux kernel, the device tree for the Bananapi M2+ has been split into a common dtsi file, and an SoC-specific board device tree file that includes both the shared dtsi file and the soc dtsi file. This was done to support both the H3 and H5 variants of the same board. This is similar to what was done for the Libre Computer ALL-H3-CC in U-boot commit d7b17f1c24af ("sunxi: Split out common board design for ALL-H3-CC device tree"). The newly split files are directly synced from Linux tag v5.0-rc1. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | | Merge branch '2019-02-29-master-imports'Tom Rini2019-02-2811-7/+12
|\ \ \ | | | | | | | | | | | | | | | | - Assorted BSP fixes - Kbuild fix
| * | | spl: add debug print for early malloc usageSimon Goldschmidt2019-02-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To find out how big the early malloc heap must be in SPL, add a debug print statement that dumps its usage before switching to relocated heap in spl_relocate_stack_gd() via CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
| * | | kbuild: fix DTB .cmd source variableStephen Warren2019-02-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | *.dts are processed using a custom command, then the C pre-processor is run on them, then they are compiled using dtc. Thus, the dependency files generated by both cpp and dtc reference a temporary file name rather than the actual source file. While this information isn't used for any purpose by the build system, and hence this causes no functional issue, it does cause the dependency files to contain invalid and confusing data, which is unhelpful while debugging build problems. Fix this using sed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | kbuild: make arch-dtbs target PHONYStephen Warren2019-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this, the arch-dtbs target only gets evaluated when building U-Boot the first time, not when re-building (incrementally building) U-Boot. Thus incremental builds ignore changes to DTB files. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | doc: binding: rename directory ram to memory-controllerPatrick Delaunay2019-02-283-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alignment with kernel directory name as it have already bindings for DDR controllers in the directory: Documentation/devicetree/bindings/memory-controller PS: the drivers using RAM u-class should be associated with this binding directory Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | | fs: fat: fix link error when building with DEBUG=1Heinrich Schuchardt2019-02-281-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiling with DEBUG=1 an error fs/fat/fat_write.c:831: undefined reference to `__aeabi_ldivmod' occurred. We should use do_div() instead of the modulus operator. filesize and cur_pos cannot be negative. So let's use u64 to avoid warnings. Fixes: cb8af8af5ba0 ("fs: fat: support write with non-zero offset") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | | arm: pdu001: Fix order of include filesFelix Brack2019-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix the order of include files according to U-Boot coding style. Signed-off-by: Felix Brack <fb@ltec.ch>
| * | | .gitignore: Ignore regenerated *.dtbo filesMichal Simek2019-02-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | *.dtbo are dt overlays files which should be also ignored as *.dtb. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: cache: Fix incorrect bitwise operationMarek Vasut2019-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The loop implemented in the code is supposed to check whether the PL310 operation register has any bit from the mask set. Currently, the code checks whether the PL310 operation register has any bit set AND whether the mask is non-zero, which is incorrect. Fix the conditional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Tom Rini <trini@konsulko.com> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
| * | | spi: omap3: fix set_wordlen() reading from incorrect address for CHCONFDavid Rivshin2019-02-281-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | _omap3_spi_set_wordlen() indexed the regs->channel[] array with the old wordlen (instead of the chipselect number) when reading the current CHCONF register value. This meant it read from the wrong memory location, modified that value, and then wrote it back to the correct CHCONF register. The end result is that most slave configuration settings would be lost, such as clock divisor, clock/chipselect polarities, etc. Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model") Signed-off-by: David Rivshin <drivshin@allworx.com>
* | | Merge git://git.denx.de/u-boot-riscvTom Rini2019-02-2733-50/+1843
|\ \ \ | | | | | | | | | | | | - SiFive FU540 Support
| * | | riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrdAnup Patel2019-02-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V because bootm will update initrd location in DTB only if CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable this option then bootm assumes DTB already has initrd details which is not the case most of the time. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
| * | | doc: Add a readme guide for SiFive FU540Atish Patra2019-02-271-0/+303
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The readme guide describes the procedure to build, flash and boot Linux using U-Boot on HiFive Unleashed. It also explains the current state of U-boot support and future action items. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
| * | | riscv: Add SiFive FU540 board supportAnup Patel2019-02-277-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | cpu: Bind timer driver for boot hartAtish Patra2019-02-271-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, timer driver is bound only for hart0. There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | drivers: serial_sifive: Skip baudrate config if no input clockAtish Patra2019-02-271-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is possible that input clock is not available because clk device was not available and 'clock-frequency' DT property is also not available. In this case, instead of failing we should just skip baudrate config by returning zero. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
| * | | drivers: serial_sifive: Fix baud rate calculationAtish Patra2019-02-271-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compute the baud rate multipler with more precision. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
| * | | clk: Add fixed-factor clock driverAnup Patel2019-02-275-2/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | clk: Add SiFive FU540 PRCI clock driverAnup Patel2019-02-278-0/+1150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de>
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