summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* arm64: mvebu: Add basic support for uDPU boardVladimir Vid2019-02-055-0/+313
| | | | | | | | | | | | | | | | | | | | | | This adds initial support for micro-DPU (uDPU) board which is based on Armada-3720 SoC. micro-DPU is the single-port FTTdp "distribution point unit" made by Methode Electronics which offers complete modularity with replaceable SFP modules both for uplink and downlink (G.hn over twisted-pair, G.hn over coax, 1G and 2.5G Ethernet over Cat-5e cable). On-board features: - 512 MiB DDR3 - 2 x 2.5G SFP via HSGMII SERDES interface to the A3720 SoC - USB 2.0 Type-C connector - 4GB eMMC - ETSI TS 101548 reverse powering via twisted pair (RJ45) or coax (F Type) Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Luis Torres <luis.torres@methode.com> Cc: Scott Roberts <scott.roberts@telus.com> Cc: Paul Arola <paul.arola@telus.com> Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* arm: mvebu: armada-xp-theadorable.dts: Enable PCIe DT nodesStefan Roese2019-02-051-0/+14
| | | | | | | | | | | | | Now that the PCIe driver supports DM and DT parsing, enable the PCIe DT nodes that are used by this board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
* arm: mvebu: armada-xp/37x.dtsi: Sync PCIe DT nodes with Linux v4.20Stefan Roese2019-02-054-30/+56
| | | | | | | | | | | | | | | | This patch sync's the PCIe DT nodes with the recent Linux v4.20 version. This change makes it easier to reference specific PCIe nodes in the board dts files to e.g. enable a PCIe port as this is now necessary with the new DM PCI driver for these platforms. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com> Cc: Tom Rini <trini@konsulko.com>
* pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfigStefan Roese2019-02-0521-217/+296
| | | | | | | | | | | | | | | | | This patch adds DM_PCI support to the MVEBU PCIe driver. This is necessary, since all PCI drivers have to be moved to DM (driver model) until the v2019.07 release. To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU from config headers to the defconfig files. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Phil Sutter <phil@nwl.cc> Cc: Marek Behún <marek.behun@nic.cz> Cc: VlaoMao <vlaomao@gmail.com>
* pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addrStefan Roese2019-02-052-9/+29
| | | | | | | | | | This function will be used by the Marvell Armada XP/38x PCIe driver, which is moved to DM right now. So let's extract the functionality from pci_uclass_child_post_bind() to make it available. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchipTom Rini2019-02-02109-6775/+7516
|\ | | | | | | | | | | | | | | u-boot-rockchip changes for 2019.04-rc1: * support for Chromebook Bob * full pinctrl driver using DTS properties * documentation improvements * I2S support for some Rockchip SoCs
| * rockchip: rk3399: spl: ensure that debug_uart_init is calledPhilipp Tomsich2019-02-011-2/+2
| | | | | | | | | | | | | | | | | | | | With the latest changes to add support for the Chromebook Bob, initialisation through debug_uart_init() did no longer get called for other targets. Fix this, by moving debug_uart_init() out of the Bob-specific Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3399-puma: enable SPL_ATF_NO_PLATFORM_PARAMPhilipp Tomsich2019-02-011-0/+1
| | | | | | | | | | | | | | | | As we're working on the next update of our ATF (and U-Boot and the ATF are out-of-sync), let's temporarily enable SPL_ATF_NO_PLATFORM_PARAM to reduce compatibility issues. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * pinctrl: Kconfig: fix missing include of rockchip/KconfigPhilipp Tomsich2019-02-011-0/+1
| | | | | | | | | | | | | | | | After the merge of the new, generic pinctrl-code, the include for rockchip/Kconfig was missing. Add it here, so we can select the pinctrl-driver for SPL. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * pinctrl: Kconfig: sort includes alphabeticallyPhilipp Tomsich2019-02-011-5/+5
| | | | | | | | | | | | | | | | To make adding new subdirectories easier, let's enforce alphabetical ordering of the includes of Kconfig files in the respective subdirectories. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add MAINTAINER entry for chromebook_speedyPhilipp Tomsich2019-02-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | This adds a MAINTAINER entry for chromebook_speedy. Without this, we get the following warnings from the maintainers check: WARNING: no status info for 'chromebook_minnie' WARNING: no maintainers for 'chromebook_minnie' Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add support for chromebook_bobSimon Glass2019-02-0110-3/+215
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bob is a 10-inch chromebook produced by Asus. It has two USB 3.0 type-C ports, 4GB of SDRAM, WiFi and a 1280x800 display. It uses its USB ports for both power and external display. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions. Support so far includes only: - UART - SDRAM - MMC, SD card - Cros EC (but not keyboard) Not included: - Keyboard - Display - Sound - USB - TPM Bob is quite similar to Kevin, the Samsung Chromebook Plus, but support for this is not provided in this series. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: gru: Add extra device-tree settingsSimon Glass2019-02-013-4/+19
| | | | | | | | | | | | | | | | Add some U-Boot-specific settings. These should really go in the *u-boot.dtsi file, but it seems that rk3399 does not use that yet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Implement spl_gpio in the GPIO driverSimon Glass2019-02-012-0/+69
| | | | | | | | | | | | | | | | | | Allow rockchip boards to use GPIOs before driver model is ready. This is really only useful for setting GPIOs to enable the early debug console, if needed on some platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Move pull-up/down enum into a common fileSimon Glass2019-02-012-7/+7
| | | | | | | | | | | | | | | | | | | | | | At present this enum is only available to rk3288. Move it so that other rockchip SoCs can access it. It is needed for the SPL GPIO driver for rk3999 in a later patch. Also adjust the enum name to lower case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3399: Add ROCKCHIP_DEVICE_SETTINGS to set envSimon Glass2019-02-011-0/+5
| | | | | | | | | | | | | | | | | | Some boards use different stdio environment variables from the default. Provide a #define for this which can be set before including the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Tidy up board include-file orderingSimon Glass2019-02-017-13/+13
| | | | | | | | | | | | | | These board files have inconsistent #include ordering. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: clk: Add mention of four new clocksSimon Glass2019-02-011-0/+12
| | | | | | | | | | | | | | | | These clocks are needed to get MMC running. We don't actually support setting them yet. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add settings for Samsung LPDDR3 4GB SDRAM 1866MHzSimon Glass2019-02-011-0/+1542
| | | | | | | | | | | | | | This memory is used on Bob. Add settings for this, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Allow booting from SPISimon Glass2019-02-011-0/+3
| | | | | | | | | | | | | | | | The u-boot,spl-boot-device property only allows MMC at present. Add SPI as well for boards that boot from SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Clarify docs on SPI writingSimon Glass2019-02-011-1/+1
| | | | | | | | | | | | | | | | | | We use every second block when creating a SPI image, so update the text to say this explicitly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: evb_rk3399: Tidy up the READMESimon Glass2019-02-011-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | Add mention of a prerequisite needed to build the image. Also adjust the English wording in a few places. Ideally this should move to using binman to produce images, and avoid the manual steps. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Adjust rk3399 device tree to be closer to linuxSimon Glass2019-02-011-61/+371
| | | | | | | | | | | | | | | | | | | | | | | | This file has changed upstream, with some additions and changes. Move the U-Boot version towards this. Some USB changes seem to be incompatible with how the bindings work on rockchip in U-Boot. Testing is needed to make sure that USB still works correct, and adjust the code (not device tree) if not. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Bring in device tree files for rk3399-gruSimon Glass2019-02-015-0/+1757
| | | | | | | | | | | | | | Bring in these files from Linux v4.20. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Drop note about supporting other SoCsSimon Glass2019-02-011-8/+1
| | | | | | | | | | | | | | | | | | Quite a wide range of Rockchip SoCs are supported in mainline U-Boot now, so drop the comment about needing to add more. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add mention of other boardsSimon Glass2019-02-011-2/+42
| | | | | | | | | | | | | | | | | | | | At present some Rockchip SoCs and boards are not mentioned in the README. So that people can see which SoCs are supported, expand the list to include everything. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * gpio: Add a simple GPIO API for SPLSimon Glass2019-02-011-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | In space-constrained environments or before driver model is available, it is sometimes necessary to set GPIO values. Add an SPL API for this, to allow early board code to change GPIOs. The caller must provide the register address, so that the drivers can be fairly generic. This API can be implemented by GPIO drivers, behind a suitable guard, like #ifdef CONFIG_SPL_BUILD. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * gpio: Use more command-specific enums valuesSimon Glass2019-02-011-14/+23
| | | | | | | | | | | | | | | | | | At present this file uses GPIO_OUTPUT and GPIO_INPUT as its sub-command values. These are pretty generic names. Add a 'C' suffix to avoid possible conflicts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * clk: Improve debug message in clk_set_default_rates()Simon Glass2019-02-011-2/+2
| | | | | | | | | | | | | | | | | | It is helpful to print the clock number as well as the index, so that this can be looked up in the binding file. Update the debug() statement to do this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * lib: Allow using display_buffer() in SPLSimon Glass2019-02-011-1/+3
| | | | | | | | | | | | | | | | | | At present this function uses printf() format strings that are not supported in SPL, so the output just consists of %llx strings on 64-bit. machines. Fix this by adding a special case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: dts: rk322x: Correct the uart2 default pin configurationDavid Wu2019-02-011-2/+9
| | | | | | | | | | | | | | | | | | | | To match the iomux setting of uart2 at SPL, correct the uart2 default pin configuration, if not changed, the evb-rk3229 can't output the log message. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * pinctrl: rockchip: Clean the unused rockchip pinctrl driversDavid Wu2019-02-019-6387/+0
| | | | | | | | | | | | | | | | | | | | | | If we used the pinctrl-rockchip driver, these code is not needed, so remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: defconfig: Clean the unused pinctrl configDavid Wu2019-02-0129-43/+20
| | | | | | | | | | | | | | | | | | If we used the pinctrl-rockchip driver, these config is not needed, so remove them. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * pinctrl: rockchip: Add common rockchip pinctrl driverDavid Wu2019-02-0115-100/+2531
| | | | | | | | | | | | | | | | | | | | Use this driver to fit all Rockchip SOCs and to support the desired pinctrl configuration via DTS. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rk3288: chrome: defconfig: Enable FDT for new pinctrl driverDavid Wu2019-02-013-6/+0
| | | | | | | | | | | | | | | | The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA and enable SPL_OF_LIBFDT to make FDT be built in. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: rockchip: Remove the pinctrl request at rk3288-board-splDavid Wu2019-02-011-79/+0
| | | | | | | | | | | | | | | | | | | | If we use the new pinctrl driver, the pinctrl setup will be done by device probe. Remove the pinctrl setup at rk3288-board-spl. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188David Wu2019-02-011-1/+0
| | | | | | | | | | | | | | | | | | | | It seems that pinctrl is not requested for rk3188 SPL, remove it so that can save more space for SPL image size. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPLDavid Wu2019-02-011-39/+2
| | | | | | | | | | | | | | | | | | When the boot ROM sets up MMC we don't need to do it again. Remove the MMC setup code entirely, but we also need to enable uart for debug message. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3399-evb: defconfig: Enable FDT for new pinctrl driverDavid Wu2019-02-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA to make FDT be built in. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: add support for veyron-speedy (ASUS Chromebook C201)Marty E. Plummer2019-02-017-1/+304
| | | | | | | | | | | | | | | | | | | | | | This adds support for the ASUS C201, a RK3288-based clamshell device. The device tree comes from linus's linux tree at 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters are for 4GB Samsung LPDDR3, decoded from coreboot's src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc Signed-off-by: Marty E. Plummer <hanetzer@startmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: dts: rk3399-firely: add 'same-as-spl'Mark Kettenis2019-02-011-1/+1
| | | | | | | | | | | | | | | | Like on rk3399-puma we want to continue booting the fill U-Boot from the same device as the SPL stage. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Drop call to rockchip_dnl_mode_check() for nowSimon Glass2019-02-011-1/+7
| | | | | | | | | | | | | | | | | | | | This function causes a 5-second delay and stops the display working on minnie. This code should be in a driver and should only be enabled by a device-tree property, so that it does not affect devices which do not have this feature. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * sound: rockchip: Add sound support for jerrySimon Glass2019-02-014-0/+21
| | | | | | | | | | | | | | | | Jerry uses a max98090 audio codec and the internal SoC I2S peripheral. Enable sound support and add the required device-tree pieces. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add a sound driverSimon Glass2019-02-012-1/+133
| | | | | | | | | | | | | | | | Add a sound driver for rk3288 supporting chromebook_jerry. This uses the I2S driver, and existing audio codec and the clock/pinmux support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: Add an I2S driverSimon Glass2019-02-013-0/+159
| | | | | | | | | | | | | | | | | | Add a driver for I2S which allows audio data to be sent from the SoC to the audio codec. The sample rate and other settings are hard-coded for now as there is no suitable device-tree binding available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass2019-02-015-0/+167
| | | | | | | | | | | | | | | | Add support for setting pinctrl and clock for I2S on rk3288. This allows the sound driver to operate. These settings were created by rkmux.py Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Merge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mipsTom Rini2019-02-0221-282/+1410
|\ \ | | | | | | | | | | | | | | | - MIPS: mscc: jr2: small fixes - MIPS: mscc: luton: add ethernet and switch driver - MIPS: mt76xx: fix timer frequency
| * | configs: mscc_luton: Add network support.Horatiu Vultur2019-02-011-0/+1
| | | | | | | | | | | | | | | | | | Update default config to use network driver for Luton SoCs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * | net: Add MSCC Luton networkd driver.Horatiu Vultur2019-02-013-0/+744
| | | | | | | | | | | | | | | | | | | | | Add network driver for Microsemi Ethernet switch, it is present on Luton SoCs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * | mips: mscc: luton: Add ethernet nodes for Luton.Horatiu Vultur2019-02-013-0/+267
| | | | | | | | | | | | | | | | | | | | | Add nodes for pcb090 and pcb091. There is currently no support in Linux for this SoC. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
View Lorry Controller Status