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* Convert CONFIG_MAC_ADDR_IN_SPIFLASH et al to KconfigAdam Ford2017-09-135-5/+27
| | | | | | | | This converts the following to Kconfig: CONFIG_MAC_ADDR_IN_SPIFLASH CONFIG_MAC_ADDR_IN_EEPROM Signed-off-by: Adam Ford <aford173@gmail.com>
* davinci: da850evm: Make EEPROM MAC code configurableAdam Ford2017-09-131-1/+4
| | | | | | | | | | | There was a check for CONFIG_MAC_ADDR_IN_EEPROM and a check for CONFIG_MAC_ADDR_IN_SPIFLASH, however some of the EEPROM related code wasn't encapsulated inside the #if defined statement so the EEPROM code could get executed even when it wasn't explicitly enabled or wanted. Signed-off-by: Adam Ford <aford173@gmail.com>
* include/configs: remove references to SMNAND_ENV_OFFSETAdam Ford2017-09-1315-44/+28
| | | | | | | | | In mancy cases both CONFIG_ENV_OFFSET and CONFIG_ENV_ADDR point to an otherwise-unused SMNAND_ENV_OFFSET. This patch will set both CONFIG_ENV_OFFSET and CONFIG_ENV_ADDR to whatever value was defined by SMNAND_ENV_OFFSET. Signed-off-by: Adam Ford <aford173@gmail.com>
* arm: dts: omap3: Re-sync DTS files with Linux 4.13-RC5Adam Ford2017-09-1313-3284/+3382
| | | | | | | | | | | | | | | | The DTS files had some spacing issues and they needed fixing. This pull re-sync's the OMAP3xx related DTS files with Linux 4.13-RC5. To keep the DTS and DTSI files clean and in sync with Linux, new u-boot.dtsi files are added. Signed-off-by: Adam Ford <aford173@gmail.com> V3: The resync broke card detect on MMC1 on Logic PD's Torpedo, so we add the cd-invert to the Torpedo's -u-boot.dtsi file. V2: Add the u-boot.dtsi files for OMAP3, OMAP36xx, and Torpedo Remove the need for the second patch in the series
* omap3: omap3_logic: Finish enabling fastboot on MUSBAdam Ford2017-09-132-1/+33
| | | | | | | | Either the USB and Fastboot were never finished, or somehow it got lost. This puts enough hooks back into omap3logic to enable fastboot and hopefully prepare it for Kconfig conversion. Signed-off-by: Adam Ford <aford173@gmail.com>
* ARM: dts: ethernut5: Fix the build warningWenyou Yang2017-09-131-0/+2
| | | | | | | | | | | | Fix the building warning as below: ---8<---- Warning (reg_format): "reg" property in /i2c-gpio-0/pcf8563@50 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /i2c-gpio-0/pcf8563@50 Warning (avoid_default_addr_size): Relying on default #size-cells value for /i2c-gpio-0/pcf8563@50 --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* serial: nulldev: Add nulldev serial driverKeng Soon Cheah2017-09-133-0/+56
| | | | | | | | | | | | | | | | Some device the serial console's initialization cannot run early during the boot process. Hence, nulldev serial device is helpful on that situation. For example, if the serial module was implemented in FPGA. Serial initialization is prohibited to run until the FPGA was programmed. This commit is to adding nulldev serial driver. This will allows the default console to be specified as a nulldev. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com> Cc: Chen Yee Chew <chen.yee.chew@ni.com>
* spl: add newline in debug outputAnatolij Gustschin2017-09-131-2/+2
| | | | | | | | With debug enabled, SPL output following these debug prints is on the same line and it is hard to read. Fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* ARM: DRA72x: Add support for detection of DRA71x SR 2.1Vishal Mahaveer2017-09-126-0/+12
| | | | | | | | | DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* davinci: da850-evm: switch to using TI_COMMON_CMD_OPTIONSAdam Ford2017-09-124-26/+37
| | | | | | | | Like the OMAP-L138 LCDK before it, let's move the da850-evm and the variations to TI_COMMON_CMD_OPTIONS to cut back one some of the defconfig entries. Signed-off-by: Adam Ford <aford173@gmail.com>
* linux/io.h: import generic ioread* / iowrite* accessors from LinuxMasahiro Yamada2017-09-121-0/+44
| | | | | | | | Some drivers in Linux (ex. drivers/mtd/nand/denali.c) use ioread*/iowrite* accessors. Import them to make drivers more synced. I copied code from include/asm-generic/io.h of Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* dma: import linux/dma-direction.h to consolidate enum dma_data_directionMasahiro Yamada2017-09-127-25/+20
| | | | | | | | Import include/linux/dma-direction.h from Linux 4.13-rc7 and delete duplicated definitions of enum dma_data_direction. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* omap3: am3517_evm: Enable TI_COMMON_CMD_OPTIONAdam Ford2017-09-122-14/+9
| | | | | | | | Enable TI_COMMON_CMD_OPTIONS and remove similar options from the defconfig. Updated with savedefconfig. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
* ARM: OMAP3: am3517_evm: Move header to ti_omap3_common.hAdam Ford2017-09-121-43/+10
| | | | | | | | | | | | Much of the AM3517 functions are copies of the standard definitions used in ti_omap3_common.h. Moving to include a common file reduces the amount of duplicative code and clutter. A few AM3517 specific functions (like EMIF4) are explictly defined and a few items are undefined or redefined, but overall the number of lines of code shink. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
* armv8: mmu: add space around operatorAndy Yan2017-09-121-1/+1
| | | | | | | | | Add space around operator "+", make it match the coding style. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: mmu: remove unused macro definitionAndy Yan2017-09-122-11/+0
| | | | | | | | | Macro VA_BITS and PTE_BLOCK_BITS are not used in the code, so remove them. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: York Sun <york.sun@nxp.com>
* cosmetic: bootcount: correct comment for used scratch registerTomas Melin2017-09-121-3/+3
| | | | Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
* misc: i2c_eeprom: Add compatible for AT24MAC402Wenyou Yang2017-09-121-0/+1
| | | | | | | | | | Add the new compatible "atmel,24mac402" to accommodate AT24MAC402. The AT24MAC402 is a 2K Serial EEPROM and the 2-Kbit memory array is internally organized as 16 pages of 16 bytes of EEPROM each. The 48-bit EUI address in the AT24MAC402 are located in the extended memory block. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* misc: i2c_eeprom: Add compatible for 24AA02E48Wenyou Yang2017-09-121-0/+1
| | | | | | | | Add the new compatible "microchip,24aa02e48" to accommodate 24AA02E48, the 24AA02E48 is a 2K I2C Serial EEPROM with pre-programmed globally unique, 48-bit node address, and 8-byte page size. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* configs: k2g_evm: Remove PMMC loading environment commandsAndrew F. Davis2017-09-121-1/+0
| | | | | | | The PMMC firmware should be bundled with the FIT image for HS devices, remove the steps that load and install this firmware outside of FIT. Signed-off-by: Andrew F. Davis <afd@ti.com>
* ARM: k2g: Add FIT image handler for PMMC firmwareAndrew F. Davis2017-09-121-0/+21
| | | | | | | | The PMMC firmware should be bundled into a FIT image on HS devices to allow authentication/decryption, add a handler to process this PMMC firmware. Signed-off-by: Andrew F. Davis <afd@ti.com>
* image: Add TI PMMC image typeAndrew F. Davis2017-09-122-0/+2
| | | | | | | Add a new image type representing TI Power Management Micro-Controller (PMMC) Firmware image type. Signed-off-by: Andrew F. Davis <afd@ti.com>
* examples: add fallback memcpyRob Clark2017-09-121-0/+12
| | | | | | | | | | | | | | | | | | | Solves build issue: Building current source for 134 boards (12 threads, 1 job per thread) arm: + lsxhl +examples/api/vsprintf.o: In function `string16': +lib/vsprintf.c:278: undefined reference to `memcpy' +examples/api/uuid.o: In function `uuid_bin_to_str': +lib/uuid.c:197: undefined reference to `memcpy' +lib/uuid.c:199: undefined reference to `memcpy' +make[3]: *** [examples/api/demo] Error 1 +make[2]: *** [examples/api] Error 2 +make[1]: *** [examples] Error 2 +make: *** [sub-make] Error 2 133 0 1 /134 sheevaplug Signed-off-by: Rob Clark <robdclark@gmail.com>
* vsprintf.c: add GUID printingRob Clark2017-09-123-2/+46
| | | | | | | | | | | | | | | | | This works (roughly) the same way as linux's, but we currently always print lower-case (ie. we just keep %pUB and %pUL for compat with linux), mostly just because that is what uuid_bin_to_str() supports. %pUb: 01020304-0506-0708-090a-0b0c0d0e0f10 %pUl: 04030201-0605-0807-090a-0b0c0d0e0f10 It will be used by a later efi_loader paths for efi variables and for device-path-to-text protocol, and also quite useful for debug prints of protocol GUIDs. Signed-off-by: Rob Clark <robdclark@gmail.com> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* vsprintf.c: add UTF-16 string (%ls) supportRob Clark2017-09-122-2/+29
| | | | | | | | | | This is convenient for efi_loader which deals a lot with UTF-16. Only enabled with CC_SHORT_WCHAR, leaving room to add a UTF-32 version when CC_SHORT_WCHAR is not enabled. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* lib: add some utf16 handling helpersRob Clark2017-09-124-14/+170
| | | | | | | We'll eventually want these in a few places in efi_loader, and also vsprintf. Signed-off-by: Rob Clark <robdclark@gmail.com>
* kbuild: Enable -fshort-wcharRob Clark2017-09-121-0/+1
| | | | | | | | | | EFI_LOADER really wants UTF-16 strings (ie. %ls and L"string" are 16bit chars instead of 32bit chars). But rather than enabling -fshort-wchar conditionally if EFI_LOADER is enabled, it was deemed preferrable to globally switch. Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-09-1267-228/+3972
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| * armv8: fsl-layerscape: Add back L3 flushing for all exception levelsYork Sun2017-09-111-4/+0
| | | | | | | | | | | | | | | | | | CCN-504 HPF registers were believed to be accessible only from EL3. However, recent tests proved otherwise. Remove checking for exception level to re-enable L3 cache flushing for all levels. Signed-off-by: York Sun <york.sun@nxp.com> Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
| * armv8: ls1088a: Enable PCIe in defconfigsHou Zhiqiang2017-09-113-0/+12
| | | | | | | | | | | | | | Enabled PCIe support and PCI command feature. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1088a: add PCIe dts nodeHou Zhiqiang2017-09-111-0/+48
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1088a: fix the MMU table for pcie config spaceHou Zhiqiang2017-09-111-0/+6
| | | | | | | | | | | | | | The pcie config space of ls1088a is different from ls2080a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Fix MC reserved memory calculationYork Sun2017-09-111-3/+12
| | | | | | | | | | | | | | | | | | In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
| * armv7: Add workaround for USB erratum A-009007Ran Wang2017-09-113-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rx Compliance tests may fail intermittently at high jitter frequencies using default register values Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: Add workaround for USB erratum A-008997Ran Wang2017-09-113-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low Frequency Periodic Singaling (LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: Add workaround for USB erratum A-009798Ran Wang2017-09-113-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receive Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: Add workaround for USB erratum A-009008Ran Wang2017-09-113-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add workaround for USB erratum A-009007Ran Wang2017-09-114-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add workaround for USB erratum A-008997Ran Wang2017-09-113-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add workaround for USB erratum A-009798Ran Wang2017-09-114-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add workaround for USB erratum A-009008Ran Wang2017-09-114-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()Ran Wang2017-09-111-0/+4
| | | | | | | | | | | | | | Some erratum patch might need it to program registers. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1088aqds: Add support of EC1 and EC2Prabhakar Kushwaha2017-09-111-0/+34
| | | | | | | | | | | | | | | | | | | | EC1 and EC2 are RGMII interface on ls1088aqds platform. This patch add support of RGMII with PHY and MDIO Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Support to add RGMII for ls1088aqdsAshish Kumar2017-09-118-1/+70
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1088aqds: Add support of LS1088AQDSAshish Kumar2017-09-1114-7/+1372
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support of LS1088AQDS platform. The LS1088A QorIQTM Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the LS1088A QorIQ Architecture processor. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1088ardb: Add support for LS1088ARDB platformAshish Kumar2017-09-1117-1/+1316
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Disabled NAND in board header file] Reviewed-by: York Sun <york.sun@nxp.com> WIP: disable NAND for LS1088ARDB
| * armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar2017-09-1116-12/+482
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Fix final MMU table for QSPI and IFCSuresh Gupta2017-09-111-2/+4
| | | | | | | | | | | | | | | | | | For QSPI and IFC addresses execution shouldn't be allowed when u-boot running from DDR. Revise the MMU final table to enforce execute-never bits. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl: Use correct conditional compile for ls1012aRan Wang2017-09-111-1/+1
| | | | | | | | | | | | | | | | | | | | According current code base, CONFIG_LS1012A should be CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be wrongly called to disable all dwc3 USB nodes on LS1012A, which cause Linux USB function stop working at all. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * drivers:net:fsl-mc: Update MC address calculationPriyanka Jain2017-09-111-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | Update MC address calculation as per MC design requirement of address as least significant 512MB address of MC private allocated memory, i.e. address should point to end address masked with 512MB offset in private DRAM block. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> [YS: reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
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