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* Merge tag 'dm-pull-18sep21' of ↵WIP/19Sep2021Tom Rini2021-09-198-180/+226
|\ | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-dm Revert the public-key-embedded-in-executable patches so this does not form part of an official release before it is agreed.
| * Revert "efi_capsule: Move signature from DTB to .rodata"Simon Glass2021-09-186-49/+4
| | | | | | | | | | | | | | | | | | | | This was unfortunately applied despite much discussion about it beiong the wrong way to implement this feature. Revert it before too many other things are built on top of it. This reverts commit ddf67daac39de76d2697d587148f4c2cb768f492. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Revert "mkeficapsule: Remove dtb related options"Simon Glass2021-09-181-7/+222
| | | | | | | | | | | | This reverts commit f86caab058ff062ce72b24cd1ab9ec1253cc1352. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Revert "doc: Update CapsuleUpdate READMEs"Simon Glass2021-09-181-124/+0
|/ | | | | | This reverts commit 316ab801c0d91c02b21b8be1e3db7e69555364e9. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch '2021-09-17-TI-platform-updates'Tom Rini2021-09-1711-131/+196
|\ | | | | | | - Assorted bugfixes for TI platforms
| * arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 ↵WIP/2021-09-17-TI-platform-updatesNishanth Menon2021-09-171-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | startup With Device Manager firmware in an elf file form, we cannot load the FIT image to the exact same address as any of the executable sections of the elf file itself is located. However, the device tree descriptions for the ARMV8 bootloader/OS includes DDR regions only the final sections in DDR where the Device Manager firmware is actually executing out of. As the R5 uC is usually operating at a slower rate than an ARMv8 MPU, by starting the Armv8 ahead of parsing the elf and copying the correct sections to the required memories creates a race condition where the ARMv8 could overwrite the elf image loaded from the FIT image prior to the R5 completing parsing and putting the correct sections of elf in the required memory locations. OR create rather obscure debug conditions where data in the section is being modified by ARMV8 OS while the elf copy is in progress. To prevent all these conditions, lets make sure that the elf parse and copy operations are completed ahead of ARMv8 being released to execute. We will pay a penalty of elf copy time, but that is a valid tradeoff in comparison to debug of alternate scenarios. Signed-off-by: Nishanth Menon <nm@ti.com>
| * arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS NorthbridgeRoger Quadros2021-09-172-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This fixup is critical to provide deterministic access latency to MSMC from ICSSG, it applies to all AM65 silicon revisions and is due to incorrect reset values (has no erratum id) and statically setting things up should be done independent of usecases and board. This specific style of Northbridge configuration is specific only to AM65x devices, follow-on K3 devices have different data prioritization schemes (ASEL and the like) and hence the fixup applies purely to AM65x. Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in case of SR1 devices, on SR2 devices, lockups were not observed so far but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower throughput. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Andrew F. Davis <afd@ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Benoit Parrot <bparrot@ti.com> [Jan: rebased, dropped used define, extended commit log] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> [Nishanth: Provide relevant context in the commit message] Signed-off-by: Nishanth Menon<nm@ti.com>
| * clk: ti: k3: Update driver to account for divider flagsSuman Anna2021-09-174-112/+118
| | | | | | | | | | | | | | | | | | | | | | | | The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-writeDave Gerlach2021-09-171-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are three different divider values in the DIV_CTRL register controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate function writes the entire register when programming plld, even though plld only resides in the lower 6 bits. Change the plld programming to read-modify-write to only affect the relevant bits for plld and to preserve the other two divider values present in the upper 16 bits, otherwise they will always get set to zero when programming plld. Fixes: 0aa2930ca192 ("clk: add support for TI K3 SoC PLL") Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: Add note to auto-generated filesDave Gerlach2021-09-174-4/+20
| | | | | | | | | | | | | | | | | | | | | | Add a note to the automatically generated clk-data and dev-data files for j721e and j7200 to indicate that they are in fact auto-generated and should not be hand edited. Also adjust TI URL to use https instead of http and also add an empty line before first header inclusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocksSuman Anna2021-09-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocksSuman Anna2021-09-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2 divisors to generate the final FOUTPOSTDIV clock. These are in sequence with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is opposite of the actual implementation. Fix the data by simply adjusting the register bit-shifts. The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0 register values, fix these as well. Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200") Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: common: Add a release_resources_for_core_shutdown() stubSuman Anna2021-09-171-0/+5
| | | | | | | | | | | | | | | | | | Add a weak release_resources_for_core_shutdown() stub implementation that can be overridden by actual implementation if a SoC supports that function. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
| * firmware: ti_sci: Include linux/err.h in ti_sci_protocol.hSuman Anna2021-09-171-1/+3
|/ | | | | | | | | | | | | | The common TI SCI header file uses some macros from err.h and these get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include the linux/err.h header file in this header file directly rather than relying on source files to include it to eliminate any potential build errors. While at this, reorder the existing header file include to the beginning of the file. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
* MAINTAINERS: POWERPC MPC8XX: Update email addressChristophe Leroy2021-09-171-1/+1
| | | | | | | | Our email addresses have changed from @c-s.fr to @csgroup.eu Update entry in MAINTAINERS Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
* Merge branch 'rpi-next' of ↵WIP/15Sep2021Tom Rini2021-09-1512-8/+44
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-raspberrypi Ivan's patch fixes a kernel warning when booting RPi2, as the firmware already provides a frambebuffer node. Marek's patch fixes random crashes on 32 bit RPi4 with newer firmware. My SMBIOS patchesfixes an issue that show up with e4f8e543f1 ("smbios: Drop the unused Kconfig options"). Basically the SMBIOS table broke and wasn't readable anymore.
| * rpi: Conditionally add simple-framebuffer nodeIvan T. Ivanov2021-09-151-6/+5
| | | | | | | | | | | | | | | | | | It appears that RPi firmware has already added framebuffer node under /chosen, at least on RPi 2 versions. So check for this and don't add duplicate node. Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * ARM: bcm283x: change the virtual address of the XHCI PCI device baseMarek Szyprowski2021-09-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the XHCI PCI device base up in the virtual address space. This fixes initialization failure observed with newer Raspberry Pi firmware, later than 63b1922311 ("firmware: arm_loader: Update armstubs with those from PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base conflicts with the updated ARM/VideoCore firmware. This also requires to reduce the size of the mapped PCI device region from 8MiB to 4MiB to fit into 32bit address space. This is still enough for the XHCI PCI device. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Tested-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * configs: rpi: Enable SMBIOS sysinfo driverMatthias Brugger2021-09-159-0/+18
| | | | | | | | | | | | | | | | Enable this driver to allow U-Boot to get SMBIOS table information from a device tree node. Signed-off-by: Matthias Brugger <mbrugger@suse.com> Acked-by: Fabian Vogt <fvogt@suse.com>
| * arm: dts: bcm283x: Add minimal smbios informationMatthias Brugger2021-09-151-0/+19
|/ | | | | | | At present SMBIOS tables are empty, which breaks some use-cases that rely on that. Add some minimal information to fulfill this. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* Prepare v2021.10-rc4v2021.10-rc4Tom Rini2021-09-141-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Resync with savedefconfigTom Rini2021-09-1427-48/+5
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* image: Avoid erroneous double byte-swap in CRC valueAlexandru Gagniuc2021-09-141-9/+0
| | | | | | | | | | | | | | | | | | | | The hash algorithm selection was streamlined in commit 92055e138f28 ("image: Drop if/elseif hash selection in calculate_hash()"). Said commit kept the call to cpu_to_uimage() to convert the CRC to big endian format. This would have been correct when calling crc32_wd(). However, the ->hash_func_ws member of crc32 points to crc32_wd_buf(), which already converts the CRC to big endian. On a little endian host, doing both conversions results in a little-endian CRC. This is incorrect. To remedy this, simply drop the call to cpu_to_uimage(), thus only doing the byte-order conversion once. Fixes: 92055e138f28 ("image: Drop if/elseif hash selection in calculate_hash()") Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
* Merge branch '2021-09-14-assorted-fixes'Tom Rini2021-09-146-21/+29
|\ | | | | | | - Assorted bugfixes
| * image: rsa: Move padding_algos to linker listsWIP/2021-09-14-assorted-fixesAlexandru Gagniuc2021-09-143-17/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are not guaranteed to have the padding_pkcs_15_verify symbol since commit 92c960bc1d ("lib: rsa: Remove #ifdefs from rsa.h"), and commit 61416fe9df ("Kconfig: FIT_SIGNATURE should not select RSA_VERIFY") The padding_algos only make sense with RSA verification, which can now be disabled in lieu of ECDSA. In fact this will lead to build failures because of the missing symbol mentioned earlier. To resolve this, move the padding_algos to a linker list, with declarations moved to rsa_verify.c. This is consistent with commit 6909edb4ce ("image: rsa: Move verification algorithm to a linker list") One could argue that the added #ifdef USE_HOSTCC is ugly, and should be hidden within the U_BOOT_PADDING_ALGO() macro. However, this would be inconsistent with the "cryptos" list. This logic for was not previously explored: Without knowledge of the U_BOOT_PADDING_ALGO() macro, its use is similar to something being declared. However, should #ifndef USE_HOSTCC be part of the macro, it would not be obvious that it behaves differently on host code and target code. Having the #ifndef outside the macro makes this obvious. Also, the #ifdef is not always necessary. For example ecda-verify makes use of U_BOOT_CRYPTO_ALGO() without any accompanying #ifdefs. The fundamental issue is a lack of separation of host and target code in rsa_verify. Therefore, the declaration of a padding algo with the external #ifdef is more readable and consistent. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
| * pinctrl: fix typoYuan Fang2021-09-141-1/+1
| | | | | | | | | | | | | | fix typo in pinctrl Kconfig file to avoid git commit failure on some commit hooks check. Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
| * lib: fix typos in KconfigOleksandr Suvorov2021-09-141-2/+2
| | | | | | | | | | | | | | | | | | | | There are trivial typos in the Kconfig file. Fixed them. Also, fixed grammar in the descriptions with typos. Fixes: d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS") Fixes: 7264f2928b ("spl: fit: Eanble GZIP support for image decompression") Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * lib/rsa: don't use NULL as key_idHeinrich Schuchardt2021-09-141-1/+1
|/ | | | | | | | | | | If keydir is not provided but name is we want to use name as key_id. But with the current coding name is only used on its own if it is NULL and keydir is provided which never occurs. Fixes: 824ee745fbca ("lib/rsa: Use the 'keyfile' argument from mkimage") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2021-09-131-3/+7
|\ | | | | | | - a fix for U-Boot 2021.10 to bring back MMC boot on older boards.
| * sunxi: mmc: A20: Fix MMC optimisationAndre Przywara2021-09-141-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the FIFO is completely full: the level size reads as zero, but the FIFO_FULL bit is set. We won't do a single iteration of the read loop in this case, so will be stuck forever. Check for this situation and use a safe minimal FIFO size instead when we hit this case. This fixes MMC boot on A20 devices after the MMC FIFO optimisation (9faae5457f52). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Merge branch '2021-09-09-finish-pre-DM_PCI-removal'WIP/13Sep2021Tom Rini2021-09-1344-2605/+36
|\ \ | |/ |/| | | - Finish removing the non-DM_PCI legacy code.
| * pci: Drop DM_PCISimon Glass2021-09-1315-54/+14
| | | | | | | | | | | | This option has not effect now. Drop it, using PCI instead where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * pci: Drop PCI_INDIRECT_BRIDGESimon Glass2021-09-1310-92/+0
| | | | | | | | | | | | This does not work with driver model so can be removed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * net: Drop DM_PCI check from designware driverSimon Glass2021-09-131-12/+10
| | | | | | | | | | | | | | | | | | We don't need this check anymore since when PCI is enabled, driver model is always used. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * pci: acpi: Drop DM_PCI check from ahciSimon Glass2021-09-132-59/+0
| | | | | | | | | | | | | | | | | | We don't need these checks anymore since when PCI is enabled, driver model is always used. Drop them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * pci: Drop DM_PCI check from fdtdecSimon Glass2021-09-131-2/+8
| | | | | | | | | | | | | | | | | | | | We don't need this check anymore since when PCI is enabled, driver model is always used. Sadly this doesn't work with nds32 for some reason to do with the toolchain. Add a work-around for that. Signed-off-by: Simon Glass <sjg@chromium.org>
| * pci: Drop old code from header fileSimon Glass2021-09-131-57/+3
| | | | | | | | | | | | | | We don't need this code anymore since when PCI is enabled, driver model is always used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * ppc: Remove UCP1020 boardSimon Glass2021-09-1316-2329/+1
|/ | | | | | | | | | | | | | | This board has not been converted to CONFIG_DM_PCI by the deadline. Remove it. Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt because it's not really migrated at this point. Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com> Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com> Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com> Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'mmc-2021-9-13' of https://source.denx.de/u-boot/custodians/u-boot-mmcTom Rini2021-09-138-25/+135
|\ | | | | | | | | | | | | | | Support using mmc command for enumerating mmc card in a given mode Fix device_remove in mmc Fix switch issue with send_status disabled Drop 1ms delay in fsl_esdhc command sending Revert "mmc: sdhci: set to INT_DATA_END when there are data"
| * mmc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()Michael Walle2021-09-131-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the beginning of this driver which was initially for the MPC8379 and MPC8536 SoCs, there is this spurious 1ms delay. According to the comment it should actually be only 8 clock cycles. Esp. during EFI block transfers, this 1ms add up to a significant delay and slows down EFI boot. I couldn't find any mention in the MPC8536 that there should be a delay of 8 clock cycles between commands. The SD card specification mentions that the clock has to be left enabled for 8 cycles after a command or response. But I don't see how this delay will help with this. Go ahead and just remove it. If there will ever be any regression we can introduce a compile time flag, but for now I'd like to keep it simple. In the split off imx driver this delay was also removed in commit 9098682200e6 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending command"). Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fix device_remove when HS400_ES is enabledYe Li2021-09-101-3/+5
| | | | | | | | | | | | | | | | HS400_ES is missed when down grade to HS mode during device_remove the mmc device Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: fix switch issue with send_status disabledYe Li2021-09-101-1/+1
| | | | | | | | | | | | | | | | When send_status is false or wait_dat0 is not supported, the switch function should not send CMD13 but directly return. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * doc: usage: mmc: Document usage of speed mode in "mmc dev" and "mmc rescan"Aswath Govindraju2021-09-101-2/+47
| | | | | | | | | | | | | | Add documentation on the usage of "mmc dev" and "mmc rescan" commands to set user defined speed modes. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
| * mmc: Add support for enumerating MMC card in a given mode using mmc commandAswath Govindraju2021-09-105-10/+81
| | | | | | | | | | | | | | | | | | | | | | | | Add support for enumerating MMC card in a given mode using mmc rescan and mmc dev commands. The speed mode is provided as the last argument in these commands and is indicated using the index from enum bus_mode in include/mmc.h. A speed mode can be set only if it has already been enabled in the device tree. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
| * Revert "mmc: sdhci: set to INT_DATA_END when there are data"Yuezhang.Mo@sony.com2021-09-101-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 17ea3c862865c0d704646f67dbf8412f9ff54f59. In eMMC specification, for the response-with-busy(R1b, R5b) command, the DAT0 will driven to LOW as BUSY status, and in sdhci specification, the transfer complete bit should be wait for BUSY status de-assert. All response-with-busy commands don't contain data, the data judgement is no need. Signed-off-by: Yuezhang.Mo <Yuezhang.Mo@sony.com> Reviewed-by: Andy Wu <Andy.Wu@sony.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Merge tag 'efi-2021-10-rc4-2' of ↵WIP/12Sep2021Tom Rini2021-09-1212-40/+88
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc4-2 Documentation: * improve documentation of U-Boot for /config DT node * integrate bloblist documentation UEFI: * correct usage of EFI_CALL() * code tidy up
| * | efi_loader: simplify efi_watchdog_timer_notify()Heinrich Schuchardt2021-09-111-2/+1
| | | | | | | | | | | | | | | | | | | | | We can call do_reset() directly without invoking the UEFI API. This decreases the code size. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | efi_loader: eliminate EFI_CALL() in nvedit_efi.cHeinrich Schuchardt2021-09-111-5/+4
| | | | | | | | | | | | | | | | | | | | | Reduce the code size by avoiding using the external UEFI API and using our internal functions instead. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | efi_loader: Remove incorrect calls of EFI_CALL in TCG2Ilias Apalodimas2021-09-111-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is two unneeded EFI_CALL references in tcg2_measure_pe_image(). The first one in efi_search_protocol() and the second on in the device path calculation. The second isn't even a function we should be calling, but a pointer assignment, which happens to work with the existing macro. While at it switch the malloc call to a calloc, remove the unnecessary cast and get rid of an unneeded if statement before copying the device path Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | efi_loader: require CONFIG_BLKHeinrich Schuchardt2021-09-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The move to driver model should by now be completed. To be able to remove pre-driver model code from our block IO code require CONFIG_BLK=y for UEFI support. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
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