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* configs: Resync with savedefconfigTom Rini2020-02-0698-175/+156
| | | | | | Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqWIP/05Feb2020Tom Rini2020-02-0575-149/+885
|\ | | | | | | | | - Bug fixes on ls1012a, ls1021a, ls1028ardb platforms Integrate fspi for ls1028a, add DM-I2C support, update secure boot header offset
| * board: ls1012ardb: do not use imply CONFIG_Heinrich Schuchardt2020-02-041-2/+2
| | | | | | | | | | | | | | | | | | Inside Kconfig we must not use the CONFIG_ prefix with the imply statement. Fixes: 28e3c39e535b ("board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: ls2088a: Updates secure boot headers offsetPriyanka Singh2020-02-042-32/+32
| | | | | | | | | | | | | | | | | | Updates the secure boot headers offsets of Kernel and other firmware images for SD and NOR boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: ls1088a: Updates secure boot headers offsetPriyanka Singh2020-02-042-33/+33
| | | | | | | | | | | | | | | | | | Updates the secure boot headers offsets of Kernel and other firmware images for SD and QSPI boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: lx2160a: Updates secure boot headers offsetPriyanka Singh2020-02-041-11/+11
| | | | | | | | | | | | | | | | | | Updates the secure boot headers offsets of Kernel and other firmware images for SD and XSPI boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: ls1012ardb: Updates secure boot headers offsetPriyanka Singh2020-02-041-1/+2
| | | | | | | | | | | | | | | | Updates the secure boot headers offsets of Kernel and other firmware images used by esbc_validate command. Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: ls1046a: Updates secure boot headers offsetPriyanka Singh2020-02-041-3/+3
| | | | | | | | | | | | | | | | | | Updates the secure boot headers offsets of Kernel and other firmware images for SD and QSPI boot sources used by esbc_validate command. Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: ls1021a: Reserve low memory for CMAAlison Wang2020-02-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The default reserved memory for CMA is high memory. If LPAE is enabled, highmem pages are non-remapped and can not be used with dma_alloc_coherent. This patch will reserve low memory for CMA and fix the issue on LS1021A. Signed-off-by: Peng Ma <peng.ma@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: arm: ls1021a: add i2c DM supportBiwen Li2020-02-0429-8/+330
| | | | | | | | | | | | | | | | This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1021A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * dm: arm64: ls1012a: add i2c DM supportBiwen Li2020-02-0421-28/+230
| | | | | | | | | | | | | | | | This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1012A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * Kconfigs: layerscape: use a convenient default value for SYS_MALLOC_F_LENBiwen Li2020-02-041-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default value of CONFIG_SYS_MALLOC_F_LEN (0x400) leaves U-Boot with not enough memory to load i2c driver before relocate, causing it to hang. Change the default value of CONFIG_SYS_MALLOC_F_LEN for below SoCs, - LS1012A - LS1021A - LS1043A - LS1046A Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * i2c: mxc_i2c: add DM_FLAG_PRE_RELOC flagBiwen Li2020-02-041-0/+1
| | | | | | | | | | | | | | | | This adds DM_FLAG_PRE_RELOC flag to probe i2c driver before relocation Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * armv8: fsl-layerscape: spl: fix build error when DM_I2C is enabledBiwen Li2020-02-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix below SPL build error when DM_I2C is enabled, - arch/arm/cpu/armv8/built-in.o: In function `board_init_f: arch/arm/cpu/armv8/fsl-layerscape/spl.c:74: undefined reference to `i2c_init_all' arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:(.text.board_init_f+0x30): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `i2c_init_all' make[2]: *** [spl/u-boot-spl] Error 1 make[1]: *** [spl/u-boot-spl] Error 2 make: *** [sub-make] Error 2 arch/arm/cpu/armv8/fsl-layerscape/spl.c: In function 'board_init_f': arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:2: warning: implicit declaration of function 'i2c_init_all'; did you mean 'misc_init_r'? [-Wimplicit-function-declaration]` Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * rtc: pcf8563: Add driver model supportBiwen Li2020-02-041-0/+107
| | | | | | | | | | | | | | Add support of driver model of pcf8563 Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: ls1028a: Enable FSPI supportKuldeep Singh2020-02-044-0/+4
| | | | | | | | | | | | | | Enable FSPI controller support. So, flash environment can now be used Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: lx2160a: Add FSPI node propertiesKuldeep Singh2020-02-042-1/+38
| | | | | | | | | | | | | | | | Align flexspi node properties with linux device-tree properties Tested on LX2160A-RDB Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: ls1028a: Add FSPI node propertiesKuldeep Singh2020-02-042-0/+31
| | | | | | | | | | | | | | | | Align flexspi node properties with linux device-tree properties Tested on LS1028A-RDB Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * board: fsl: lx2160a: Add support to reset to eMMCMeenakshi Aggarwal2020-02-044-0/+10
| | | | | | | | | | | | | | Add support of "qixis_reset emmc" command for lx2160a based platforms Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: dts: ls1028a: fix interrupt propertiesMichael Walle2020-02-041-24/+31
| | | | | | | | | | | | | | | | | | | | | | Sync the interrupt properties with the ones from Linux. Also use the constants provided by the dt-bindings header. Please note, that there are actual changes/fixes in the irq flags. U-Boot won't use the interrupt properties anyway. It's just to be consistent with the Linux device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * arm: ls1028a: use the new flexspi driverMichael Walle2020-02-041-6/+8
| | | | | | | | | | | | | | | | Also align the fspi node with the kernel one. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * configs: ls1012ardb: Enable CONFIG_SYS_RELOC_GD_ENV_ADDRKuldeep Singh2020-02-044-0/+4
| | | | | | | | | | | | | | | | Enable the config for ls1012ardb as the entry got missed earlier. Fixes: 8d8ee47e03 ("env: Add CONFIG_SYS_RELOC_GD_ENV_ADDR symbol") Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | Merge tag 'rpi-next-2020.04' of ↵Tom Rini2020-02-0511-45/+854
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - DFU support file operations lager then the default max size - add dfu support to dwc2 for bcm2835 - enable DFU for RPi4 - Fix RPi4 memory map to include the genet device - add driver for the genet ethernet device - enable network support in RPi4 config
| * | rpi4: Enable GENET Ethernet controllerAmit Singh Tomar2020-01-293-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Raspberry Pi 4 SoC features an integrated Gigabit Ethernet controller, connected as a platform device. Enable the new driver in the three applicable defconfigs, to allow TFTP booting on the board. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> [Andre: Add joined and 32-bit configs] Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * | rpi4: Update memory map to accommodate scb devicesAmit Singh Tomar2020-01-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the devices(for instance, pcie and gnet controller) sitting on SCB bus falls behind/below the memory range that we currenty have. This patch updates the memory range to map those devices correctly. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * | net: Add support for Broadcom GENETv5 Ethernet controllerAmit Singh Tomar2020-01-293-0/+737
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Broadcom GENET Ethernet MACs are used in several MIPS based SoCs and in the Broadcom 2711/2838 SoC used on the Raspberry Pi 4. There is no publicly available documentation, so this driver is based on the Linux driver. Compared to that the queue management is drastically simplified, also we only support version 5 of the IP and RGMII connections between MAC and PHY, as used on the RPi4. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: heavy cleanup and a few fixes] Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * | config: enable DFU over USB on Raspberry Pi4 boardsMarek Szyprowski2020-01-293-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for DFU over USB. This requires to enable USB gadget, DWC2 UDC OTG driver and DFU command. DFU entities are defined for the following firmware objects: u-boot.bin, uboot.env, config.txt, and zImage/Image. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * | usb: dwc2_udc_otg: add bcm2835 SoC (Raspberry Pi4) supportMarek Szyprowski2020-01-292-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Broadcom 2835 SoC requires special conversion of physical memory addresses for DMA purpose, so add needed wrappers to dwc2_udc_otg driver. Also extend the list of compatible devices with 'brcm,bcm2835-usb' entry. This allows to use USB gadget drivers (i.e. DFU) on Raspberry Pi4 boards. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * | dfu: mmc: remove file size limit for io operationsMarek Szyprowski2020-01-291-16/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for operations on files larger than CONFIG_SYS_DFU_MAX_FILE_SIZE. The buffered io mechanism is still used for aggregating io requests, so for files up to CONFIG_SYS_DFU_MAX_FILE_SIZE nothing is changed and they will be handled in a single filesystem call. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
| * | dfu: mmc: rearrange the codeMarek Szyprowski2020-01-291-27/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename functions for bufferred file io operations to make them easier to understand. Also add missing file offset argument to them (currently unused). All this is a preparation to remove predefined file size limit (CONFIG_SYS_DFU_MAX_FILE_SIZE) for DFU read/write operations. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Lukasz Majewski <lukma@denx.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86WIP/04Feb2020Tom Rini2020-02-0426-157/+308
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Various minor fixes for x86 - Switch to ACPI mode on Intel edison - Support run-time configuration for NS16550 driver - Update coreboot and slimbootloader serial drivers to use NS16550 run-time configuration - ICH SPI driver fixes to hardware sequencing erase case - Move ITSS from Apollo Lake to a more generic location - Intel GPIO driver bug fixes - Move to vs2017-win2016 platform build host for Azure pipelines
| * | | azure: Move to vs2017-win2016 platform build hostTom Rini2020-02-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Azure is moving to remove the vs2015-win2012r2 platform build host. The two suggested new platforms to use are vs2017-win2016 and windows-2019. For now, move up to vs2017-win2016. Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value()Wolfgang Wallner2020-02-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following in intel_gpio_get_value(): * The value of the register is contained in the variable 'reg', not in 'mode'. The variable 'mode' contains only the configuration whether the gpio is currently an input or an output. * The correct bitmasks for the input and output value are PAD_CFG0_RX_STATE and PAD_CFG0_TX_STATE. Use them instead of the currently used PAD_CFG0_RX_STATE_BIT and PAD_CFG0_TX_STATE_BIT. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | gpio: intel_gpio: Clear tx state bit when setting outputWolfgang Wallner2020-02-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing 'PAD_CFG0_TX_STATE' to the clear mask for pcr_clrsetbits32(). Otherwise this bit cannot be cleared again after it has been set once. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32()Wolfgang Wallner2020-02-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function pcr_clrsetbits32() expects a device with a P2SB parent device. In intel_gpio_direction_output() and intel_gpio_set_value() the device 'dev' is passed to pcr_clrsetbits32(), which is a gpio-controller with a device 'pinctrl' as parent. This does not match the expectations of pcr_clrsetbits32(). But the 'pinctrl' device has a P2SB as parent. Pass the 'pinctrl' device instead of the 'dev' device to pcr_clrsetbits32(). Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: itss: Remove apl-prefixWolfgang Wallner2020-02-042-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so remove the apl-prefix of the implemented functions/structures/... Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: itss: Add a Kconfig option to enable/disable ITSS driverWolfgang Wallner2020-02-043-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Kconfig option to support enabling/disabling the inclusion of the ITSS driver depending on the platform. Atuomatically select the ITSS driver when building for Apollo Lake. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232761/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: Move itss.c from Apollo Lake to a more generic locationWolfgang Wallner2020-02-043-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Interrupt Timer Subsystem (ITSS) is not specific to Apollo Lake, so move it to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: conditionally build itss.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: Move itss.h from Apollo Lake to the generic x86 include directoryWolfgang Wallner2020-02-043-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code in this file is not specific to Apollo Lake. According to coreboot sources (where this code comes from), it is common to at least: * Apollo Lake * Cannon Lake * Ice Lake * Skylake Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: apl: Add the term "Interrupt Timer Subsystem" to ITSS filesWolfgang Wallner2020-02-042-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ITSS stands for "Interrupt Timer Subsystem", so add that term to the description of the relevant files. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | spi: ich: Drop while loop in hardware sequencing erase caseWolfgang Wallner2020-02-041-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When ich_spi_exec_op_hwseq() is called to erase a 4k block (opcode = SPINOR_OP_BE_4K), it expects to find a length value in op->data.nbytes, but that value is always 0. As a result, the while loop is never executed and no erase is carried out. Fix this by dropping the loop code entirely, only keeping the relevant parts of the loop body. See http://patchwork.ozlabs.org/patch/1222779/ for more detailed background information and discussion. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: edison: Switch to ACPI modeAndy Shevchenko2020-02-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SFI is quite poor and useless resource provider. Moreover it makes hard to develop and extend functionality in the Linux kernel. Enable a necessary minimum to use ACPI on Intel Edison. Linux kernel have been prepared for this change since v5.4, where the last crucial driver, i.e. for Basin Cove PMIC, has been submitted. Note, that stock image won't suffer by this change since it doesn't have ACPI enabled on the kernel level. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: edison: Enable command line editingMarek Vasut2020-02-041-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable command line editing, because it is extremely convenient. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | doc: Chromebook Coral: fix build warningsHeinrich Schuchardt2020-02-041-44/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use valid restructured text to avoid warnings like WARNING: Title underline too short. WARNING: Block quote ends without a blank line; unexpected unindent. when building with `make htmldocs`. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: limit the fs segment to the pointer sizeMasahiro Yamada2020-02-041-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fs segment is only used to get the global data pointer. If it is accessed beyond sizeof(new_gd->arch.gd_addr), it is a bug. To specify the byte-granule limit size, drop the G bit, so the flag field is 0x8093 instead of 0xc093, and set the limit field to sizeof(new_gd->arch.gd_addr) - 1. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed the comments about FS segement] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: use invd instead of wbinvd in real mode start codeMasahiro Yamada2020-02-042-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I do not know why the boot code immediately after the system reset should write-back the cache content. I think the cache invalidation should be enough. I tested this commit with qemu-x86_defconfig, and it worked for me. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | doc: intel: Update serial driver changes in slimbootloader.rstPark, Aiden2020-02-041-27/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, Slim Bootloader uses NS16550_DYNAMIC to support serial port configuration at runtime, so no more code change is required. Therefore, remove unnecessary steps and fix minor typo. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: serial: Use NS16550_DYNAMIC in Slim BootloaderPark, Aiden2020-02-042-21/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Slim Bootloader provides serial port info in its HOB to support both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32 or SYS_NS16550_PORT_MAPPED in U-Boot. To support both serial port configurations dynamically at runtime, Slim Bootloader serial driver leverages NS16550_DYNAMIC. Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: remove the obsolete comments for data->type] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: Move coreboot over to use the coreboot UARTSimon Glass2020-02-041-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use this UART to improve the compatibility of U-Boot when used as a coreboot payload. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: serial: Add a coreboot serial driverSimon Glass2020-02-043-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coreboot can provide information about the serial device in use on a platform. Add a driver that uses this information to produce a working UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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