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* sunxi: usb: Switch to Generic host controllersJagan Teki2019-01-18105-26/+99
| | | | | | | | | | | | | | Onc of key blocker for using USB Generic host controller drivers in Allwinner are CLK and RESET drivers, now these available for USB usage. So switch sunxi USB use EHCI and OHCI Generic controllers. Enabling USB is wisely a board choise, So Enable USB_OHCI_HCD where it already have USB_EHCI_HCD Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* musb-new: sunxi: Use CLK and RESET supportJagan Teki2019-01-181-40/+39
| | | | | | | | | Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Marek Vasut <marex@denx.de>
* reset: Add reset validJagan Teki2019-01-181-0/+11
| | | | | | | | Add reset_valid to check whether given reset is valid or not. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* phy: sun4i-usb: Use CLK and RESET supportJagan Teki2019-01-181-20/+57
| | | | | | | | | Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Marek Vasut <marex@denx.de>
* arm: sunxi: Enable CLK, RESETJagan Teki2019-01-181-0/+1
| | | | | | | | | CLK and DM_RESET drivers are now available for all of the Allwinner platforms, so enable them in arch/arm/Kconfig Enabling CLK will select DM_RESET by default. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* sunxi: A64: Update sun50i-a64-ccu.hJagan Teki2019-01-181-0/+2
| | | | | | | | | | | | | | | | | | Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree: commit 679294497be31596e1c9c61507746d72b6b05f26 Author: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz> Date: Wed Sep 26 19:48:24 2018 +0000 arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay This should be a part of previous sync patch from commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691 Author: Andre Przywara <andre.przywara@arm.com> Date: Mon Oct 29 00:56:47 2018 +0000 sunxi: A64: Update .dts/.dtsi files Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* clk: sunxi: Add Allwinner A80 CLK driverJagan Teki2019-01-183-0/+65
| | | | | | | | | | | | | Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3Jagan Teki2019-01-1810-471/+1597
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update all A80 devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commits. arch/arm/boot/dts/sun9i-a80*: commit 190e3138f9577885691540dca59c2f07540bde04 Merge: cafc87023b0d a7affb13b271 Author: Arnd Bergmann <arnd@arndb.de> Date: Tue Mar 27 14:58:00 2018 +0200 Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt include/dt-bindings/*/sun9i-a80-*: commit 783ab76ae553abc23f80ef7511052d055697531b Author: Chen-Yu Tsai <wens@csie.org> Date: Sat Jan 28 20:22:36 2017 +0800 clk: sunxi-ng: Add A80 Display Engine CCU Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same dts is not available in Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* clk: sunxi: Add Allwinner H6 CLK driverJagan Teki2019-01-183-0/+61
| | | | | | | | | | | | | | Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* clk: sunxi: Implement UART resetsJagan Teki2019-01-187-0/+43
| | | | | | | | Implement UART resets for all relevant Allwinner SoC clock drivers via ccu reset table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* clk: sunxi: Implement UART clocksJagan Teki2019-01-189-0/+57
| | | | | | | | Implement UART clocks for all Allwinner SoC clock drivers via ccu clock gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* clk: sunxi: Add Allwinner V3S CLK driverJagan Teki2019-01-183-0/+59
| | | | | | | | | | | | | | Add initial clock driver for Allwinner V3S. - Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* clk: sunxi: Add Allwinner R40 CLK driverJagan Teki2019-01-183-0/+78
| | | | | | | | | | | | | | Add initial clock driver for Allwinner R40. - Implement USB bus and USB clocks via ccu_clk_gate for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* clk: sunxi: Add Allwinner A83T CLK driverJagan Teki2019-01-183-0/+71
| | | | | | | | | | | | | | Add initial clock driver for Allwinner A83T. - Implement USB bus and USB clocks via ccu_clk_gate table for A83T, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A83T, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* clk: sunxi: Add Allwinner A23/A33 CLK driverJagan Teki2019-01-183-0/+71
| | | | | | | | | | | | | | Add initial clock driver for Allwinner A23/A33. - Implement USB bus and USB clocks via ccu_clk_gate table for A23/A33, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A23/A33, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* clk: sunxi: Add Allwinner A31 CLK driverJagan Teki2019-01-183-0/+76
| | | | | | | | | | | | | | Add initial clock driver for Allwinner A31. - Implement USB ahb1 and USB clocks via ccu_clk_gate table for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB ahb1 and USB resets via ccu_reset table for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* clk: sunxi: Add Allwinner A10s/A13 CLK driverJagan Teki2019-01-183-0/+64
| | | | | | | | | | | | | | Add initial clock driver for Allwinner A10s/A13. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* clk: sunxi: Add Allwinner A10/A20 CLK driverJagan Teki2019-01-183-0/+67
| | | | | | | | | | | | | | Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* clk: sunxi: Add Allwinner H3/H5 CLK driverJagan Teki2019-01-183-0/+87
| | | | | | | | | | | | | | Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* reset: Add Allwinner RESET driverJagan Teki2019-01-186-1/+186
| | | | | | | | | | | | | | | | Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* clk: Add Allwinner A64 CLK driverJagan Teki2019-01-187-0/+214
| | | | | | | | | | | Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
* board: sun50i-h5: Add Emlid Neutis N5 supportAleksandr Aleksandrov2019-01-185-0/+299
| | | | | | | | | | | | | | | Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT module, DDR3 RAM and eMMC. - add neutis-devboard target to dtb makefile - add dtsi file for Neutis N5 needs - add config file for Neutis N5 Dev board Signed-off-by: Aleksandr Aleksandrov <aleksandr.aleksandrov@emlid.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: update proper commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* sunxi: board: Add i2c initialization for sun50iStefan Mavrodiev2019-01-182-0/+15
| | | | | | | | | | | | | | | To use TWI0/1/2 the user can select CONFIG_I2C#_ENABLE. However even the controller is enabled, the mux for the pins are not set. This patch follows the existing mux method. Since the pads are different, separate check is added for each i2c. Tested with A64-SOM204 board. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* Merge tag 'mips-pull-2019-11-16' of git://git.denx.de/u-boot-mipsTom Rini2019-01-1790-496/+2907
|\ | | | | | | | | | | | | | | | | | | - MIPS: mscc: various enhancements for Luton and Ocelot platforms - MIPS: mscc: added support for Jaguar2 platform - MIPS: optimised SPL linker script - MIPS: bcm6368: fix restart flow issues - MIPS: fixed CONFIG_OF_EMBED warnings for all MIPS boards - MIPS: mt7688: small fixes and enhancements - mmc: compile-out write support if disabled
| * mips: mt7688: gardena-smart-gateway: Enable green power LED on startupStefan Roese2019-01-161-1/+1
| | | | | | | | | | | | | | Set the correct power-up state (default-state) of the green power LED. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: mt7688: gardena-smart-gateway: Update mtdparts/mtdids for Kernel 4.19Stefan Roese2019-01-162-4/+4
| | | | | | | | | | | | | | | | | | With the new SPI NOR framework in v4.19, we need to adapt the MTD parts so that the kernel cmdline parameter "mtdparts=" uses the correct naming for the devices. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: bmips: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck2019-01-1611-11/+0
| | | | | | | | | | | | | | | | | | Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Based on https://patchwork.ozlabs.org/patch/1019791/ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: xilfpga: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck2019-01-161-1/+0
| | | | | | | | | | | | Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: pic32mzdask: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck2019-01-161-1/+0
| | | | | | | | | | | | Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: malta: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck2019-01-164-4/+0
| | | | | | | | | | | | Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: boston: switch to CONFIG_OF_SEPARATEDaniel Schwierzeck2019-01-168-8/+0
| | | | | | | | | | | | Fix the Kconfig warning to not use CONFIG_OF_EMBED in defconfigs. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MSCC: Add board support for Jaguar2 SOC familyHoratiu Vultur2019-01-169-24/+232
| | | | | | | | | | | | | | Add board support and configuration for Jaguar2 SOC family. The detection of the board type in this family is based on the phy ids. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * MSCC: add device tree for Serval2 boardHoratiu Vultur2019-01-162-0/+61
| | | | | | | | | | | | Add device tree based on evaluation board pcb112. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * MSCC: Add device tree for Jaguar2-48 boardHoratiu Vultur2019-01-161-0/+74
| | | | | | | | | | | | Add device tree based on evaluation board pcb111. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * MSCC: Add device tree for Jaguar2 boardHoratiu Vultur2019-01-163-0/+262
| | | | | | | | | | | | Add device tree based on evaluation board pcb110. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * MSCC: Add support for Jaguar2 SOC familyHoratiu Vultur2019-01-1610-8/+460
| | | | | | | | | | | | | | As the Ocelot and Luton SoCs, this family of SoCs are found in Microsemi Switches solution. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC familyHoratiu Vultur2019-01-168-29/+444
| | | | | | | | | | | | | | | | The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common to support new numbe of pins and remove any platform dependency from mscc-common. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
| * mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.cLars Povlsen2019-01-163-130/+0
| | | | | | | | | | | | | | | | With the new mscc_bb_spi.c driver, there is no longer use for the gpio-mscc-bitbang-spi.c driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: mscc: DT: Update luton device tree to use fast SPI driverLars Povlsen2019-01-162-14/+4
| | | | | | | | | | | | | | | | | | | | Thes patch change the luton base device tree to use the newly added SPI bitbang driver. It also updates the "mscc_luton_defconfig" to use the new driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: spi: mscc: Add fast bitbang SPI driverLars Povlsen2019-01-165-0/+283
| | | | | | | | | | | | | | | | | | | | This patch add a new SPI driver for MSCC SOCs that does not sport the designware SPI hardware controller. Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mmc: jz_mmc: Compile-out write support if disabledEzequiel Garcia2019-01-161-44/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not build write support, unless it's enabled. In the SPL case, this change will typically remove precious bytes (as write support is most often not needed in SPL). This is important on this platform, where the maximum SPL size is 14 KiB. With gcc v7.3, this change saves 144 bytes producing: size spl/u-boot-spl text data bss dec hex filename 9240 752 712 10704 29d0 spl/u-boot-spl To make the code easier to compile-out and more readable, a pair of read_data/write_data helpers are created. Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mmc: Use proper IS_ENABLED macro to check block supportEzequiel Garcia2019-01-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_IS_ENABLED(BLK) instead of CONFIG_BLK, in order to fix the following build issues when CONFIG_SPL_MMC_WRITE is selected: drivers/mmc/mmc_write.c:69:7: error: conflicting types for 'mmc_berase' ulong mmc_berase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt) ^~~~~~~~~~ In file included from drivers/mmc/mmc_write.c:15:0: drivers/mmc/mmc_private.h:39:7: note: previous declaration of 'mmc_berase' was here ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt); ^~~~~~~~~~ drivers/mmc/mmc_write.c:187:7: error: conflicting types for 'mmc_bwrite' ulong mmc_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, ^~~~~~~~~~ In file included from drivers/mmc/mmc_write.c:15:0: drivers/mmc/mmc_private.h:37:7: note: previous declaration of 'mmc_bwrite' was here ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, ^~~~~~~~~~ Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * net: bcm6368: fix restart flow issuesÁlvaro Fernández Rojas2019-01-161-47/+62
| | | | | | | | | | | | | | Correctly enable/disable bcm6368-net controller to avoid flow issues. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: jz47xx: remove custom u-boot-spl.ldsDaniel Schwierzeck2019-01-162-51/+0
| | | | | | | | | | | | | | | | | | There is no real difference between the generic variant and the custom variant except that the generic variant is more optimised. This also saves 24 Bytes in the SPL binary. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
| * MIPS: optimize and fix ELF sectionsDaniel Schwierzeck2019-01-162-68/+136
| | | | | | | | | | | | | | | | | | | | | | Discard ABI related sections which are not required for debugging. Rearrange debug sections similar to Linux. Remove the remaining explicitely specified sections in the unused part because those sections are not created anymore or because the linker puts them by default at the end of the ELF binary. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Ezequiel Garcia <ezequiel@collabora.com>
| * mips: ocelot: Enable use of serial gpio for LEDLars Povlsen2019-01-162-0/+9
| | | | | | | | | | | | | | This enables the use of the MSCC serial GPIO driver to control the LEDs on the MSCC VCoreIII 'ocelot' pcb123 and pcb120. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
| * mips: ocelot: DT: Enable use of serial gpioLars Povlsen2019-01-163-0/+124
| | | | | | | | | | | | | | | | This enables the use of the MSCC serial GPIO driver on the MSCC VCoreIII 'ocelot' SOC, and add gpio-leds nodes to the pcb123 and pcb120 DT. Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
| * mips: luton: Enable use of serial gpio for LEDLars Povlsen2019-01-162-0/+9
| | | | | | | | | | | | | | This enables the use of the MSCC serial GPIO driver to control the LEDs on the MSCC VCoreIII 'luton' SoC. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
| * mips: luton: DT: Enable use of serial gpioLars Povlsen2019-01-163-0/+68
| | | | | | | | | | | | | | This enables the use of the MSCC serial GPIO driver, and add gpio-leds nodes to the 'luton' pcb090 and pcb091 DT. Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com>
| * mips: mscc_sgpio: Add DT bindings documentationLars Povlsen2019-01-161-0/+45
| | | | | | | | | | | | | | | | This add device tree binding documentation for the MSCC serial GPIO driver. Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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