summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* board: MCR3000: Activate CONFIG_DM and CONFIG_OF_CONTROLChristophe Leroy2018-12-034-0/+22
| | | | | | Add mcr3000 device tree and activate CONFIG_DM and CONFIG_OF_CONTROL Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* powerpc, mpc8xx: clear top of stackChristophe Leroy2018-12-031-1/+3
| | | | | | Reported-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com>
* test: vboot: clean its filePhilippe Reynes2018-12-039-69/+69
| | | | | | | | | This update the its file used in vboot test to respect the new node style name defined in doc/uImage.FIT (for example: replace kernel@1 by kernel and fdt@1 by fdt-1) Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* test: vboot: add padding pss for rsa signaturePhilippe Reynes2018-12-035-5/+187
| | | | | | | | The padding pss is now supported for rsa signature. This add test with padding pss on vboot test. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* configs: sandbox: enable padding pss for rsa signaturePhilippe Reynes2018-12-031-0/+1
| | | | | Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* doc: uImage.FIT: signature.txt: add option paddingPhilippe Reynes2018-12-031-0/+3
| | | | | Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rsa: add support of padding pssPhilippe Reynes2018-12-036-0/+230
| | | | | | | | We add the support of the padding pss for rsa signature. This new padding is often recommended instead of pkcs-1.5. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rsa: add a structure for the paddingPhilippe Reynes2018-12-037-23/+116
| | | | | | | | | | The rsa signature use a padding algorithm. By default, we use the padding pkcs-1.5. In order to add some new padding algorithm, we add a padding framework to manage several padding algorithm. The choice of the padding is done in the file .its. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rsa: use new openssl API to create signaturePhilippe Reynes2018-12-031-6/+11
| | | | | | | | | | Previous implementation of the rsa signature was using the openssl API EVP_Sign*, but the new openssl API EVP_DigestSign* is more flexible. So we move to this new API. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rtc: m41t62: Convert the RTC driver to support the driver model (DM)Lukasz Majewski2018-12-031-0/+77
| | | | | | | | After this change the m41t62.c can be used with RTC subsystem (i.e. date command) which uses device model (DM). Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* rtc: m41t62: Extract common RTC handling code to facilitate DM conversionLukasz Majewski2018-12-031-12/+20
| | | | | | | | This change facilitates the conversion of m41t62 RTC driver to device model (DM). Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* rtc: m41t62: Break i2c_write() arguments to fix checkpatch warningLukasz Majewski2018-12-031-1/+2
| | | | | | | No functional change for this commit. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
* Kconfig: Migrate CONFIG_RTC_M41T62 define to KconfigLukasz Majewski2018-12-039-4/+10
| | | | | | | | This patch moves the RTC M41T62 config define to Kconfig. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* eeprom: Add device model based I2C support to eeprom commandLukasz Majewski2018-12-031-3/+21
| | | | | | After this change the 'eeprom' command can be used with DM aware boards. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* arm: baltos: migrate Ethernet PHYs configuration to KconfigYegor Yefremov2018-12-032-4/+2
| | | | | | | | Remove CONFIG_PHY_ATHEROS and CONFIG_PHY_SMSC from defconfig and select them in Kconfig. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: baltos: move CONFIG_SYS_NAND_U_BOOT_OFFS to defconfigYegor Yefremov2018-12-032-8/+3
| | | | | | | | Also get rid of CONFIG_SYS_NAND_SPL_KERNEL_OFFS as SPL_OS_BOOT feature won't be used. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: baltos: remove unused headerYegor Yefremov2018-12-031-1/+0
| | | | | | | | OnRISC Baltos series uses SoM with tps65910 PMIC, so remove "power/tps65217.h" header inclusion. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: baltos: move the board to CONFIG_BLKYegor Yefremov2018-12-034-15/+447
| | | | | | | | | | | Use DM for both MMC and USB subsystems and use dedicated DTS for U-Boot configuration. Disable SPL support for GPIO and remove EVMSK leftover for DDR power control via GPIO. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'u-boot-amlogic-20181203' of git://git.denx.de/u-boot-amlogicTom Rini2018-12-039-66/+151
|\ | | | | | | ARM: meson: Add regmap support for clock driver and sync DT with 4.19
| * ARM: meson: Add regmap support for clock driverLoic Devulder2018-12-039-66/+151
| | | | | | | | | | | | | | | | | | | | | | This patch modifies the meson clock driver to use syscon/regmap like the Linux kernel does, as it is needed if we want to share the same DTS files. DTS files are synchronized from Linux 4.19. Signed-off-by: Loic Devulder <ldevulder@suse.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com>
* | Merge tag 'arc-updates-for-2019.01-rc1' of git://git.denx.de/u-boot-arcTom Rini2018-12-037-49/+274
|\ \ | |/ |/| | | | | | | | | | | We introduce much better automatic identification of ARC cores. 1. Try to match found HW features to known ARC core templates 2. Print CPU frequency for all ARC boards 3. Add more board-specific info
| * arc: devboards: Implement checkboard()Alexey Brodkin2018-12-033-0/+24
| | | | | | | | | | | | This allows us to print nice board name on boot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: emsdp: Refactor register and bit accessesAlexey Brodkin2018-12-031-9/+9
| | | | | | | | | | | | | | | | | | Instead of "base + offset" define all registers right away and access them later via direct defines. Generate bit masks with "BIT" macro. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: emsdp: Read real CPU clock value from hardwareAlexey Brodkin2018-12-031-3/+39
| | | | | | | | | | | | | | | | | | | | | | | | We do real CPU clock measurement with help of built-in counters. Thus we may accommodate different real clock values that appear in different FPA images instead of relying on something hard-coded in the .dtb. And while at it make make SDIO base address define look similar to others with casting to "(void *)". Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: Get rid of board-specific print_cpuinfo()Alexey Brodkin2018-12-032-18/+0
| | | | | | | | | | | | | | | | Since we now do advanced CPU identification in generic ARC code there's no need to have per-board hardcoded data. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * ARC: Improve identification of ARC coresAlexey Brodkin2018-12-032-21/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Try to guess a ARC core template that was used i.e. not just name a core family but something more menaingful like "ARC HS38", "ARC EM11D" etc. We do it checking availability of the key differentiation features like: - Caches (we actually only check for L1 I$ fpr simplicity) - XY-memory - DSP extensions etc. 2. Identify ARC subsystems 3. Print core clock frequency Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * arc: emsdp: Bump RAM size to 16 MbAlexey Brodkin2018-12-031-1/+1
|/ | | | | | | | | | On v2 boards that will hit real stock we'll have 16 Mb of RAM. Note on v1 boards (if anybody ever get one out of trash bin) this leads to U-Boot execution freeze in the middle ofthe relocation so don't be surprised. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* drivers: rtc: correctly convert seconds to time structureHeinrich Schuchardt2018-12-011-1/+5
| | | | | | | | | Variable 'days' must be defined as signed int. Otherwise the conversion fails for some dates, e.g. 2004-08-25. Cf function rtc_time64_to_tm() in the Linux kernel source. Fixes: 992c1db45591 "drivers: rtc: resolve year 2038 problem in rtc_to_tm" Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* Merge tag 'for-master-20181130' of git://git.denx.de/u-boot-rockchipTom Rini2018-12-0121-200/+1542
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Improvements: - RK3188 USB-UART functionality - errors triggering a hard-stop in SPL on the RK3399 are reported - Rockchip RV1108 (SoC) support - MicroCrystal RV3029 (RTC) DM driver Fixes: - RK3188 early UART setup - limit SD-card frequency to 40MHz on the RK3399-Q7 - MIPI fixes - RK3399 CPUB clock initialisation
| * rockchip: rk3188: use board_debug_uart_init() for UART io initKever Yang2018-11-302-11/+18
| | | | | | | | | | | | | | | | Sync with other rockchip SoCs, use board_debug_uart_init() to init default UART iomux. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3399: Initialize CPU B clock.Christoph Muellner2018-11-302-13/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch sets the PLL of CPU cluster B (BPLL) to 600 MHz. This decreases the boot time of Linux 4.19 by about 8%. The 600 MHz are inspired by the 600 MHz used for LPLL initialization (came in with commit 9f636a249c1). Tested on RK3399-Q7 on Haikou base board. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rtc: rv3029: update to support DM and sync with Linux 4.17Philipp Tomsich2018-11-302-138/+443
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "Flamingo" carrier-board for the RK3399-Q7 has a RV3029 populated and the application will use the off-module RV3029 RTC including the battery backed SRAM. To support this use case, this commit includes the following changes: * updates the rv3029 driver to use DM * implements the read8/write8 operations This syncs the implementation with the Linux code (based on 4.17), porting the trickle-charger support from there (with improvements to avoid unnecessary EEPROM updates) and adheres to the Linux DTS binding. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
| * rtc: rv3029: add to KconfigPhilipp Tomsich2018-11-301-0/+10
| | | | | | | | | | | | | | | | The MicroCrystal RV3029 driver didn't have a Kconfig entry and was not used anywhere. Add it to Kconfig to make it selectable. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
| * ARM: rockchip: rv1108: Add support for default distro_bootcmdOtavio Salvador2018-11-302-0/+18
| | | | | | | | | | | | | | | | | | | | | | This allow easier integration of RV1108 based boards on generic distributions and build systems. To avoid behavior change, we make evb-rv1108 to use the existing environment as it boots from its SPI NOR. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: dts: rockchip: Add rv1108 USB OTG pinctrlOtavio Salvador2018-11-301-3/+42
| | | | | | | | | | | | | | | | | | This adds the definitions need to use the USB OTG in rv1108 board. This has been tested using USB Mass Storage to export and program a eMMC device. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: rockchip: rv1108: Add a board_usb_init for USB OTGOtavio Salvador2018-11-302-0/+82
| | | | | | | | | | | | | | | | Like it is done for other Rockchip SoCs, introduce a board_usb_init() function so that USB OTG can be functional on rv1108 too. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: dts: rockchip: Add rv1108 eMMC pinctrlOtavio Salvador2018-11-301-0/+29
| | | | | | | | | | | | | | | | This adds the pinctrl handles to enable the use of eMMC on custom boards (as minievk) and makes it easier for later addition. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: rockchip: rv1108: Enable BOUNCE_BUFFEROtavio Salvador2018-11-301-0/+3
| | | | | | | | | | | | | | | | | | | | In order to be able to build the Rockchip eMMC driver on rv1108, the BOUNCE_BUFFER option needs to be selected. Select it like it is done on the other Rockchip SoC common files. Reviewed-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * ARM: rockchip: rv1108: Sync clock with vendor treeOtavio Salvador2018-11-304-33/+729
| | | | | | | | | | | | | | | | Make adjustments to the rv1108 clock driver in order to align it with the internal Rockchip version. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3399-puma: reduce sd card max-frequency to 40MHzPhilipp Tomsich2018-11-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SanDisk Ultra cards trigger intermittent errors on detection resulting in an -EOPNOTSUPP, when running at 50MHz. Waveform analysis suggest that the level shifters that are used on the RK3399-Q7 module (for voltage translation between the on-module voltages and the 3.3V required on the card-edge) don't handle clock rates at or above 48MHz properly. This change reduces the maximum frequency on the external SD-interface to 40MHz (for a safety margin of 20%). Reported-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
| * rockchip: rock: remove TPL_TINY_MEMSETKever Yang2018-11-301-1/+0
| | | | | | | | | | | | | | | | | | | | The RK3188 rock board does not need TPL: remove TPL_TINY_MEMSET from config. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed up commit message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3399: spl: always report errors triggering a hard stopPhilipp Tomsich2018-11-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The RK3399 SPL has two cases that may end in a hard-stop: if either the pinctrl can not be initialised or if the DRAM fails to initialise. Both have previously not triggered an error message unless DEBUG was defined (i.e. both used debug() to print the error). This converts both error messages to be printed using pr_err() to ensure that some output points to the cause of the hard-stop. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: video: mipi: Fix phy frequency settingRichard Röjfors2018-11-301-1/+1
| | | | | | | | | | | | | | | | | | | | There was an incorrect check when looping and finding the first fast enough frequency in the freq_rang table. The code did actually return the first that was either exactly correct or too slow. Signed-off-by: Richard Röjfors <richard@puffinpack.se> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: video: mipi: Do not write to the version registerRichard Röjfors2018-11-301-1/+1
| | | | | | | | | | | | | | | | There was a copy and paste error where the data enable setting was written to the version register. Signed-off-by: Richard Röjfors <richard@puffinpack.se> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3188: fix early uart setupHeiko Stuebner2018-11-301-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") moved the iomux settings out of the grf header to prevent conflicts with the iomux definitions of other rockchip socs. This also breaks the early uart setup, as the iomux for uart2 are needed. To fix that just put the tiny amount of needed iomux definitions next to the early uart code. Fixes: 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * rockchip: rk3188: add support for usb-uart functionalityHeiko Stuebner2018-11-303-4/+73
| | | | | | | | | | | | | | | | | | | | | | Rockchip socs can route the debug uart pins through the d+ and d- pins of one specific usbphy per soc. Add a config option and implement the setting on the rk3188. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed up to mark grf as maybe unused:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* | Merge tag 'pull-30nov18' of git://git.denx.de/u-boot-dmTom Rini2018-11-3071-679/+1284
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | Fix sound on sandbox Convert TPM fully to DM Tidy up sandbox I2C emulation Add a 'make qcheck' target for faster testing A few other misc things (dropped the final patch which breaks clang for some reason)
| * | core: ofnode: Fix ofnode_get_addr_index functionKeerthy2018-11-291-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | Currently the else part of ofnode_get_addr_index function does not fetch addresses based on the index but rather just returns the base address. Fix that. Signed-off-by: Keerthy <j-keerthy@ti.com>
| * | tpm: Convert to use a device parameterSimon Glass2018-11-2917-431/+731
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present many TPM calls assume there is only one TPM in the system and look up this TPM themselves. This is inconsistent with driver model, which expects all driver methods to have a device parameter. Update the code to correct this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | tpm: Export the open/close functionsSimon Glass2018-11-293-38/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present these functions are not accessible outside the TPM library, but in some cases we need to call them. Export them in the header file and add a define for the SHA1 digest size. Also adjust tpm_open() to call tpm_close() first so that the TPM is in a known state before opening (e.g. by a previous phase of U-Boot). Signed-off-by: Simon Glass <sjg@chromium.org>
View Lorry Controller Status